1.
Bratan, Costin Andrei; Marinescu, Andreea; Terecoasa, Elena; Tebeanu, Ana Voichita; Morosanu, Bogdan; Franti, Eduard; Dascalu, Monica; Andrei, Alexandra; Tocila-Matasel, Claudia; Ionescu, Bogdan; Iana, Gheorghe; Oproiu, Ana Maria; Iorgulescu, Gabriela
In: INTERNATIONAL JOURNAL OF EDUCATION AND INFORMATION TECHNOLOGIES, vol. 19, pp. 120-127, 2025, ISSN: 2074-1316.
Abstract | Links | BibTeX | Tags: artificial voice for education; convolutional neural network; emotion intensity detection; learning outcomes; magnetic resonance imaging; mirror neurons; mirror neurons; timbre recognition
@article{WOS:001550462000001,
title = {Mirror Neurons cannot be Fooled by Artificial Voices - a study with
Implications for Education using Magnetic Resonance Imaging (MRI) and
Convolutional Neural Network (CNN)},
author = {Costin Andrei Bratan and Andreea Marinescu and Elena Terecoasa and Ana Voichita Tebeanu and Bogdan Morosanu and Eduard Franti and Monica Dascalu and Alexandra Andrei and Claudia Tocila-Matasel and Bogdan Ionescu and Gheorghe Iana and Ana Maria Oproiu and Gabriela Iorgulescu},
doi = {10.46300/9109.2025.19.12},
issn = {2074-1316},
year = {2025},
date = {2025-01-01},
journal = {INTERNATIONAL JOURNAL OF EDUCATION AND INFORMATION TECHNOLOGIES},
volume = {19},
pages = {120-127},
publisher = {NORTH ATLANTIC UNIV UNION-NAUN},
address = {991 US Highway 22, Suite 100, Bridewater, New Jersey, UNITED STATES},
abstract = {Mirror neurons have a crucial role in detecting and reproducing the
actions of others as if the observer himself were performing the
specific action. In this paper, four different audio voice files are
used to determine, in two methods, the idea that the mirror neurons can
be activated only by aAreal human original voice with a strong emotional
load. The first method is the magnetic resonance imaging (MRI), which
gives information about the brain activity regarding the specific areas
where the mirror neurons are located when the four different audio files
are listened to by a group ofAten volunteers. The second method implies
a deep learning approach, using two convolutional neural network (CNNs)
architectures, one used to recognize the timbre of the audio speaker and
the second one to determine the level of remnant (residual) emotion in
the audio files listened to by them. The four audio files used are an
audio text recorded by a Romanian actress with a specific emotion, two
different actresses' voice recordings with the same text and emotion,
and with very similar voice features to the main actress, and the last
one is an artificially generated voice using AI algorithm. The results
show a promising response from both perspectives-the hypothesis that
mirror neurons can't be fooled by an artificial voice is confirmed, and
that the intensity of emotion is higher in the original voice than the
two imitating voices.},
keywords = {artificial voice for education; convolutional neural network; emotion intensity detection; learning outcomes; magnetic resonance imaging; mirror neurons; mirror neurons; timbre recognition},
pubstate = {published},
tppubtype = {article}
}
Mirror neurons have a crucial role in detecting and reproducing the
actions of others as if the observer himself were performing the
specific action. In this paper, four different audio voice files are
used to determine, in two methods, the idea that the mirror neurons can
be activated only by aAreal human original voice with a strong emotional
load. The first method is the magnetic resonance imaging (MRI), which
gives information about the brain activity regarding the specific areas
where the mirror neurons are located when the four different audio files
are listened to by a group ofAten volunteers. The second method implies
a deep learning approach, using two convolutional neural network (CNNs)
architectures, one used to recognize the timbre of the audio speaker and
the second one to determine the level of remnant (residual) emotion in
the audio files listened to by them. The four audio files used are an
audio text recorded by a Romanian actress with a specific emotion, two
different actresses' voice recordings with the same text and emotion,
and with very similar voice features to the main actress, and the last
one is an artificially generated voice using AI algorithm. The results
show a promising response from both perspectives-the hypothesis that
mirror neurons can't be fooled by an artificial voice is confirmed, and
that the intensity of emotion is higher in the original voice than the
two imitating voices.
actions of others as if the observer himself were performing the
specific action. In this paper, four different audio voice files are
used to determine, in two methods, the idea that the mirror neurons can
be activated only by aAreal human original voice with a strong emotional
load. The first method is the magnetic resonance imaging (MRI), which
gives information about the brain activity regarding the specific areas
where the mirror neurons are located when the four different audio files
are listened to by a group ofAten volunteers. The second method implies
a deep learning approach, using two convolutional neural network (CNNs)
architectures, one used to recognize the timbre of the audio speaker and
the second one to determine the level of remnant (residual) emotion in
the audio files listened to by them. The four audio files used are an
audio text recorded by a Romanian actress with a specific emotion, two
different actresses' voice recordings with the same text and emotion,
and with very similar voice features to the main actress, and the last
one is an artificially generated voice using AI algorithm. The results
show a promising response from both perspectives-the hypothesis that
mirror neurons can't be fooled by an artificial voice is confirmed, and
that the intensity of emotion is higher in the original voice than the
two imitating voices.
2.
Popescu, Mihai; Ravariu, Cristian; Hascsi, Zoltan
First and Second Order Digital Circuits with Neuronal Models under Pulses Train Stimulus Journal Article
In: ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, vol. 28, no. 2, pp. 223-232, 2025, ISSN: 1453-8245.
Abstract | Links | BibTeX | Tags: Circuits; flip-flop; logic block; neurons; pulses train
@article{WOS:001538680900010,
title = {First and Second Order Digital Circuits with Neuronal Models under
Pulses Train Stimulus},
author = {Mihai Popescu and Cristian Ravariu and Zoltan Hascsi},
doi = {10.59277/ROMJIST.2025.2.09},
issn = {1453-8245},
year = {2025},
date = {2025-01-01},
journal = {ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY},
volume = {28},
number = {2},
pages = {223-232},
publisher = {EDITURA ACAD ROMANE},
address = {CALEA 13 SEPTEMBRIE NR 13, SECTOR 5, BUCURESTI 050711, ROMANIA},
abstract = {One or more neurons can be perceived as an analog circuit in terms of
their voltage-time characteristics, but at the block level, they can
rather fulfill a logic function. This later approach is imposed by the
neuron membrane behavior that always works between two voltage levels -
the resting potential and the acting potential, easily associated to two
binary states. These levels change when an appropriate combination of
pulses trains appears on the neuron's exciting and inhibiting input
synapses. Being difficult to describe in all details the neuronal
processes inside the human brain, this paper proposes some digital
models able to mimic these biological processes. The first original
element of this paper is the extension of the neuronal models,
previously presented, from 0-order logic circuits to 1-order logic and
2-order logic circuits. The envelope signal shelters the pulses train
that stimulate any neuron, and this envelope signal signature as the
digital function represents an element of originality.},
keywords = {Circuits; flip-flop; logic block; neurons; pulses train},
pubstate = {published},
tppubtype = {article}
}
One or more neurons can be perceived as an analog circuit in terms of
their voltage-time characteristics, but at the block level, they can
rather fulfill a logic function. This later approach is imposed by the
neuron membrane behavior that always works between two voltage levels -
the resting potential and the acting potential, easily associated to two
binary states. These levels change when an appropriate combination of
pulses trains appears on the neuron's exciting and inhibiting input
synapses. Being difficult to describe in all details the neuronal
processes inside the human brain, this paper proposes some digital
models able to mimic these biological processes. The first original
element of this paper is the extension of the neuronal models,
previously presented, from 0-order logic circuits to 1-order logic and
2-order logic circuits. The envelope signal shelters the pulses train
that stimulate any neuron, and this envelope signal signature as the
digital function represents an element of originality.
their voltage-time characteristics, but at the block level, they can
rather fulfill a logic function. This later approach is imposed by the
neuron membrane behavior that always works between two voltage levels -
the resting potential and the acting potential, easily associated to two
binary states. These levels change when an appropriate combination of
pulses trains appears on the neuron's exciting and inhibiting input
synapses. Being difficult to describe in all details the neuronal
processes inside the human brain, this paper proposes some digital
models able to mimic these biological processes. The first original
element of this paper is the extension of the neuronal models,
previously presented, from 0-order logic circuits to 1-order logic and
2-order logic circuits. The envelope signal shelters the pulses train
that stimulate any neuron, and this envelope signal signature as the
digital function represents an element of originality.
3.
Vasile, Costin-Emanuel; Ulmamei, Andrei-Alexandru; Bira, Calin
Image Processing Hardware Acceleration-A Review of Operations Involved and Current Hardware Approaches Journal Article
In: JOURNAL OF IMAGING, vol. 10, no. 12, 2024.
Abstract | Links | BibTeX | Tags: image processing; neural networks; hardware accelerators; FPGA
@article{WOS:001386823200001,
title = {Image Processing Hardware Acceleration-A Review of Operations Involved
and Current Hardware Approaches},
author = {Costin-Emanuel Vasile and Andrei-Alexandru Ulmamei and Calin Bira},
doi = {10.3390/jimaging10120298},
year = {2024},
date = {2024-12-01},
journal = {JOURNAL OF IMAGING},
volume = {10},
number = {12},
publisher = {MDPI},
address = {MDPI AG, Grosspeteranlage 5, CH-4052 BASEL, SWITZERLAND},
abstract = {This review provides an in-depth analysis of current hardware
acceleration approaches for image processing and neural network
inference, focusing on key operations involved in these applications and
the hardware platforms used to deploy them. We examine various
solutions, including traditional CPU-GPU systems, custom ASIC designs,
and FPGA implementations, while also considering emerging low-power,
resource-constrained devices.},
keywords = {image processing; neural networks; hardware accelerators; FPGA},
pubstate = {published},
tppubtype = {article}
}
This review provides an in-depth analysis of current hardware
acceleration approaches for image processing and neural network
inference, focusing on key operations involved in these applications and
the hardware platforms used to deploy them. We examine various
solutions, including traditional CPU-GPU systems, custom ASIC designs,
and FPGA implementations, while also considering emerging low-power,
resource-constrained devices.
acceleration approaches for image processing and neural network
inference, focusing on key operations involved in these applications and
the hardware platforms used to deploy them. We examine various
solutions, including traditional CPU-GPU systems, custom ASIC designs,
and FPGA implementations, while also considering emerging low-power,
resource-constrained devices.
4.
Vasile, Costin-Emanuel; Bîră, Călin; Popescu, George-Vlădut
XTEA Brute-Force Cracker for FPGA in HLS and HDL Proceedings Article
In: 2024 International Symposium on Electronics and Telecommunications (ISETC), pp. 1-4, 2024, ISSN: 2475-7861.
Abstract | Links | BibTeX | Tags: Graphics processing units;Companies;C++ languages;Benchmark testing;Encryption;Telecommunications;Power dissipation;Hardware design languages;Field programmable gate arrays;XTEA;brute-force cracker;FPGA;HLS;HDL
@inproceedings{10797331,
title = {XTEA Brute-Force Cracker for FPGA in HLS and HDL},
author = {Costin-Emanuel Vasile and Călin Bîră and George-Vlădut Popescu},
doi = {10.1109/ISETC63109.2024.10797331},
issn = {2475-7861},
year = {2024},
date = {2024-11-01},
booktitle = {2024 International Symposium on Electronics and Telecommunications (ISETC)},
pages = {1-4},
abstract = {This work presents a study comparing Extended Tiny Encryption Algorithm (XTEA) brute-force cracker C++/hlsand Verilog/HDL implementations on FPGA. The HDL-based implementation outperformed the HLS-based implementation by a factor of 2.8, and it also demonstrated exceptionally low total power dissipation compared to both CPU and GPU implementations.},
keywords = {Graphics processing units;Companies;C++ languages;Benchmark testing;Encryption;Telecommunications;Power dissipation;Hardware design languages;Field programmable gate arrays;XTEA;brute-force cracker;FPGA;HLS;HDL},
pubstate = {published},
tppubtype = {inproceedings}
}
This work presents a study comparing Extended Tiny Encryption Algorithm (XTEA) brute-force cracker C++/hlsand Verilog/HDL implementations on FPGA. The HDL-based implementation outperformed the HLS-based implementation by a factor of 2.8, and it also demonstrated exceptionally low total power dissipation compared to both CPU and GPU implementations.
5.
Vasile, Costin-Emanuel; Bîră, Călin; Popescu, George-Vlădut
TEA/XTEA Brute-Force Cracker for CPU, GPU and FPGA Proceedings Article
In: 2024 International Semiconductor Conference (CAS), pp. 249-252, 2024, ISSN: 2377-0678.
Abstract | Links | BibTeX | Tags: Art;Graphics processing units;C++ languages;Parallel processing;Benchmark testing;Encryption;Kernel;Field programmable gate arrays;TEA;XTEA;brute-force cracker;FPGA;GPU;CPU
@inproceedings{10736715,
title = {TEA/XTEA Brute-Force Cracker for CPU, GPU and FPGA},
author = {Costin-Emanuel Vasile and Călin Bîră and George-Vlădut Popescu},
doi = {10.1109/CAS62834.2024.10736715},
issn = {2377-0678},
year = {2024},
date = {2024-10-01},
booktitle = {2024 International Semiconductor Conference (CAS)},
pages = {249-252},
abstract = {This work presents a study comparing Tiny Encryption Algorithm (TEA/XTEA) brute-force cracker C++ implementations on FPGA, GPU and CPU. Our HLS FPGA implementation outperformed by at least 2.5x core-per-core state-of-the art for TEA and 20x for XTEA. For a similar 75W TDP, our FPGA implementation outperformed our GPU implementation by at least 3x.},
keywords = {Art;Graphics processing units;C++ languages;Parallel processing;Benchmark testing;Encryption;Kernel;Field programmable gate arrays;TEA;XTEA;brute-force cracker;FPGA;GPU;CPU},
pubstate = {published},
tppubtype = {inproceedings}
}
This work presents a study comparing Tiny Encryption Algorithm (TEA/XTEA) brute-force cracker C++ implementations on FPGA, GPU and CPU. Our HLS FPGA implementation outperformed by at least 2.5x core-per-core state-of-the art for TEA and 20x for XTEA. For a similar 75W TDP, our FPGA implementation outperformed our GPU implementation by at least 3x.
6.
Margineanu, Teodor; Enescu, Horia-Razvan; Vasile, Costin-Emanuel; Enachescu, Marius
Cryptography Core Implementation Starting From Open-Source RTL Proceedings Article
In: 2024 International Semiconductor Conference (CAS), pp. 253-256, 2024, ISSN: 2377-0678.
Abstract | Links | BibTeX | Tags: Industries;Protocols;Encryption;IP networks;AES;open-source;RTL;UVM;physical design
@inproceedings{10736862,
title = {Cryptography Core Implementation Starting From Open-Source RTL},
author = {Teodor Margineanu and Horia-Razvan Enescu and Costin-Emanuel Vasile and Marius Enachescu},
doi = {10.1109/CAS62834.2024.10736862},
issn = {2377-0678},
year = {2024},
date = {2024-10-01},
booktitle = {2024 International Semiconductor Conference (CAS)},
pages = {253-256},
abstract = {The chip shortage and demand for skilled workers have driven the adoption of open-source tools and IP reuse in the industry. This paper presents the design and implementation of a low power, small area IC encryption core, based on the AES protocol. Starting from open-source RTL modules, such as the CPU, the AES and the UART, three buffers and a peripheral adapter have been designed to enable the entire crypto-system integration (AESCRYPT), hence enabling the system to serve as a central hub for data encrypt within a larger framework. By developing the UVM-based verification environment, the AESCRYPT system was verified before and after implementation in a 65nm technology, demonstrating its full functionality.},
keywords = {Industries;Protocols;Encryption;IP networks;AES;open-source;RTL;UVM;physical design},
pubstate = {published},
tppubtype = {inproceedings}
}
The chip shortage and demand for skilled workers have driven the adoption of open-source tools and IP reuse in the industry. This paper presents the design and implementation of a low power, small area IC encryption core, based on the AES protocol. Starting from open-source RTL modules, such as the CPU, the AES and the UART, three buffers and a peripheral adapter have been designed to enable the entire crypto-system integration (AESCRYPT), hence enabling the system to serve as a central hub for data encrypt within a larger framework. By developing the UVM-based verification environment, the AESCRYPT system was verified before and after implementation in a 65nm technology, demonstrating its full functionality.
7.
Popescu, Mihai; Zoltan, Hascsi; Srinivasulu, Avireni; Doncu, Roxana Elena; Ravariu, Cristian
Simulation of Logic Circuits Using Bursting Neuron Models Proceedings Article
In: 2024 International Semiconductor Conference (CAS), pp. 195-198, 2024, ISSN: 2377-0678.
Abstract | Links | BibTeX | Tags: Logic circuits;Neurons;Voltage;Logic gates;Logic functions;Brain modeling;Generators;Logic;Integrated circuit modeling;Synapses;circuit;neuron;logic;gate;pulses train
@inproceedings{10736729,
title = {Simulation of Logic Circuits Using Bursting Neuron Models},
author = {Mihai Popescu and Hascsi Zoltan and Avireni Srinivasulu and Roxana Elena Doncu and Cristian Ravariu},
doi = {10.1109/CAS62834.2024.10736729},
issn = {2377-0678},
year = {2024},
date = {2024-10-01},
booktitle = {2024 International Semiconductor Conference (CAS)},
pages = {195-198},
abstract = {A neuron can be perceived as analog circuit in terms of voltage-time characteristics. Sometimes, at function level, it can be rather considered a logic circuit. This later approach is not so indefensible because the neuron membrane always works between two voltage levels, immediately associated by a binary logic. These levels are changing at a certain group of pulses on its exciting or inhibiting input synapses. Being hard to describe exactly the neural calculus processes inside the human brain we create some models able to mimic these processes. In this paper we proposed some neuronal models able to implement logic gates. The envelope signal shelters the pulses train that stimulate any neuron, and this envelope signal ensure the digital function, as a main element of originality.},
keywords = {Logic circuits;Neurons;Voltage;Logic gates;Logic functions;Brain modeling;Generators;Logic;Integrated circuit modeling;Synapses;circuit;neuron;logic;gate;pulses train},
pubstate = {published},
tppubtype = {inproceedings}
}
A neuron can be perceived as analog circuit in terms of voltage-time characteristics. Sometimes, at function level, it can be rather considered a logic circuit. This later approach is not so indefensible because the neuron membrane always works between two voltage levels, immediately associated by a binary logic. These levels are changing at a certain group of pulses on its exciting or inhibiting input synapses. Being hard to describe exactly the neural calculus processes inside the human brain we create some models able to mimic these processes. In this paper we proposed some neuronal models able to implement logic gates. The envelope signal shelters the pulses train that stimulate any neuron, and this envelope signal ensure the digital function, as a main element of originality.
8.
Busu, Iulian; Enescu, Alexandra-Mihaela; Enescu, Horia-Răzvan; Bîră, Călin
Using ChatGPT to write program-space optimized source-code Proceedings Article
In: 2024 Advanced Topics on Measurement and Simulation (ATOMS), pp. 279-282, 2024.
Abstract | Links | BibTeX | Tags: Embedded systems;Optimizing compilers;Microcontrollers;Source coding;Writing;Chatbots;Timing;Resource management;Artificial intelligence;Optimization;ChatGPT;Microcontroller;Embedded System;Binary-Size Optimization
@inproceedings{10921548,
title = {Using ChatGPT to write program-space optimized source-code},
author = {Iulian Busu and Alexandra-Mihaela Enescu and Horia-Răzvan Enescu and Călin Bîră},
doi = {10.1109/ATOMS60779.2024.10921548},
year = {2024},
date = {2024-08-01},
booktitle = {2024 Advanced Topics on Measurement and Simulation (ATOMS)},
pages = {279-282},
abstract = {This work presents an exploratory study of how ChatGPT, the AI assistant developed by OpenAI, can support engineers in developing C and ASM code for low-cost, memory-constrained microcontrollers (PIC10F200). We evaluated ChatGPT’s ability to assist with writing the source code and found that it demonstrated to deliver faster results with competitive performance levels for C language, in almost ready-to-run programs, provided that the specific timings and resource allocation is performed by an optimizing compiler. In ASM however, ChatGPT was barely adequate, its performance being lower than average young engineers, despite intensive help received from an experienced human programmer.},
keywords = {Embedded systems;Optimizing compilers;Microcontrollers;Source coding;Writing;Chatbots;Timing;Resource management;Artificial intelligence;Optimization;ChatGPT;Microcontroller;Embedded System;Binary-Size Optimization},
pubstate = {published},
tppubtype = {inproceedings}
}
This work presents an exploratory study of how ChatGPT, the AI assistant developed by OpenAI, can support engineers in developing C and ASM code for low-cost, memory-constrained microcontrollers (PIC10F200). We evaluated ChatGPT’s ability to assist with writing the source code and found that it demonstrated to deliver faster results with competitive performance levels for C language, in almost ready-to-run programs, provided that the specific timings and resource allocation is performed by an optimizing compiler. In ASM however, ChatGPT was barely adequate, its performance being lower than average young engineers, despite intensive help received from an experienced human programmer.
9.
Margineanu, Teodor; Enescu, Alexandra-Mihaela; Enescu, Horia-Razvan; Enachescu, Marius
NTP-Synchronized Time-Stamper for RADAR Signal Acquisition Proceedings Article
In: 2024 IEEE International Black Sea Conference on Communications and Networking (BlackSeaCom), pp. 119-124, 2024, ISSN: 2687-9808.
Abstract | Links | BibTeX | Tags: Accuracy;Microcontrollers;Spaceborne radar;Surveillance;Operating systems;Sea measurements;Aerospace electronics;Embedded System;NTP;Time-stamper;RADAR
@inproceedings{10646303,
title = {NTP-Synchronized Time-Stamper for RADAR Signal Acquisition},
author = {Teodor Margineanu and Alexandra-Mihaela Enescu and Horia-Razvan Enescu and Marius Enachescu},
doi = {10.1109/BlackSeaCom61746.2024.10646303},
issn = {2687-9808},
year = {2024},
date = {2024-06-01},
booktitle = {2024 IEEE International Black Sea Conference on Communications and Networking (BlackSeaCom)},
pages = {119-124},
abstract = {This work presents a hardware implementation of the NTP-synchronized time-stamper for RADAR signal acquisition which has significantly enhanced the precision and robustness of the Cheia ground-based FMCW space radar system. By utilizing a bare-metal STM32 microcontroller for on-demand synchronization and data management, the system now ensures accurate time alignment and seamless information transfer to the controlling computer. This solution not only addresses accuracy challenges, but also may optimize the radar system's tracking capabilities. The successful integration of the time-stamper device might underscore its value in improving data acquisition and analysis, marking a significant advancement in space surveillance and tracking technologies.},
keywords = {Accuracy;Microcontrollers;Spaceborne radar;Surveillance;Operating systems;Sea measurements;Aerospace electronics;Embedded System;NTP;Time-stamper;RADAR},
pubstate = {published},
tppubtype = {inproceedings}
}
This work presents a hardware implementation of the NTP-synchronized time-stamper for RADAR signal acquisition which has significantly enhanced the precision and robustness of the Cheia ground-based FMCW space radar system. By utilizing a bare-metal STM32 microcontroller for on-demand synchronization and data management, the system now ensures accurate time alignment and seamless information transfer to the controlling computer. This solution not only addresses accuracy challenges, but also may optimize the radar system's tracking capabilities. The successful integration of the time-stamper device might underscore its value in improving data acquisition and analysis, marking a significant advancement in space surveillance and tracking technologies.
10.
Popescu, George-Vlăduţ; Antonescu, Mihai; Enescu, Alexandra-Mihaela; Mărgineanu, Teodor
Evaluation of DarkNet19 and DarkNet53 Inference Time on CPU, GPU, and FPGA Proceedings Article
In: 2024 IEEE 18th International Symposium on Applied Computational Intelligence and Informatics (SACI), pp. 000163-000168, 2024, ISSN: 2765-818X.
Abstract | Links | BibTeX | Tags: Power demand;Accuracy;Object detection;Speech recognition;Machine learning;Hardware;Silicon;Convolutional Neural Networks;DarkNet19;DarkNet53;CPU;GPU;FPGA
@inproceedings{10619919,
title = {Evaluation of DarkNet19 and DarkNet53 Inference Time on CPU, GPU, and FPGA},
author = {George-Vlăduţ Popescu and Mihai Antonescu and Alexandra-Mihaela Enescu and Teodor Mărgineanu},
doi = {10.1109/SACI60582.2024.10619919},
issn = {2765-818X},
year = {2024},
date = {2024-05-01},
booktitle = {2024 IEEE 18th International Symposium on Applied Computational Intelligence and Informatics (SACI)},
pages = {000163-000168},
abstract = {The Convolutional Neural Networks used in machine learning applications such as handwriting recognition, object detection, or speech recognition are dealing with large amounts of data, thus requiring high computing capabilities. To meet this need, various hardware solutions have been proposed and are being rapidly improved. Choosing a hardware platform that offers the most effective support, whether it's speed, accuracy, or power consumption, becomes very important. In this paper, the inference time for DarkNet19 and DarkNet53, two convolutional neuronal networks used in object detection, is evaluated on a selection of CPUs, GPUs, and FPGAs.},
keywords = {Power demand;Accuracy;Object detection;Speech recognition;Machine learning;Hardware;Silicon;Convolutional Neural Networks;DarkNet19;DarkNet53;CPU;GPU;FPGA},
pubstate = {published},
tppubtype = {inproceedings}
}
The Convolutional Neural Networks used in machine learning applications such as handwriting recognition, object detection, or speech recognition are dealing with large amounts of data, thus requiring high computing capabilities. To meet this need, various hardware solutions have been proposed and are being rapidly improved. Choosing a hardware platform that offers the most effective support, whether it's speed, accuracy, or power consumption, becomes very important. In this paper, the inference time for DarkNet19 and DarkNet53, two convolutional neuronal networks used in object detection, is evaluated on a selection of CPUs, GPUs, and FPGAs.
11.
Ulmamei, Andrei-Alexandru; Bira, Calin
An Approach for Implementing Electronic Image Stabilization Using an FPGA System Journal Article
In: ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, vol. 27, no. 3-4, pp. 267-280, 2024, ISSN: 1453-8245.
Abstract | BibTeX | Tags: Electronic image stabilization; Field Programmable Gate Array; System on Chip
@article{WOS:001339559600002,
title = {An Approach for Implementing Electronic Image Stabilization Using an
FPGA System},
author = {Andrei-Alexandru Ulmamei and Calin Bira},
issn = {1453-8245},
year = {2024},
date = {2024-01-01},
journal = {ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY},
volume = {27},
number = {3-4},
pages = {267-280},
publisher = {EDITURA ACAD ROMANE},
address = {CALEA 13 SEPTEMBRIE NR 13, SECTOR 5, BUCURESTI 050711, ROMANIA},
abstract = {This paper proposes an approach for the implementation of a low-power
electronic (digital) image stabilization using an AMD/Xilinx Zynq
UltraScale+ ZU7EV device (CPU+FPGA) with a custom Linux OS. The
stabilization method is based on frame-to-frame motion detection (Harris
Corner Detector, an iterative optical flow calculator combined with a
4:2:1 down-sampler an 1:2:4 up-sampler) and an affine transformation
that applies the stabilization. The scientific contribution of this
paper resides in a combination of the most recent software algorithms
presented in literature and porting that new resulting algorithm into
hardware with the achieved performance of more than 2.5x current state
of the art, thus enabling stabilization at 4K-UHD resolution.},
keywords = {Electronic image stabilization; Field Programmable Gate Array; System on Chip},
pubstate = {published},
tppubtype = {article}
}
This paper proposes an approach for the implementation of a low-power
electronic (digital) image stabilization using an AMD/Xilinx Zynq
UltraScale+ ZU7EV device (CPU+FPGA) with a custom Linux OS. The
stabilization method is based on frame-to-frame motion detection (Harris
Corner Detector, an iterative optical flow calculator combined with a
4:2:1 down-sampler an 1:2:4 up-sampler) and an affine transformation
that applies the stabilization. The scientific contribution of this
paper resides in a combination of the most recent software algorithms
presented in literature and porting that new resulting algorithm into
hardware with the achieved performance of more than 2.5x current state
of the art, thus enabling stabilization at 4K-UHD resolution.
electronic (digital) image stabilization using an AMD/Xilinx Zynq
UltraScale+ ZU7EV device (CPU+FPGA) with a custom Linux OS. The
stabilization method is based on frame-to-frame motion detection (Harris
Corner Detector, an iterative optical flow calculator combined with a
4:2:1 down-sampler an 1:2:4 up-sampler) and an affine transformation
that applies the stabilization. The scientific contribution of this
paper resides in a combination of the most recent software algorithms
presented in literature and porting that new resulting algorithm into
hardware with the achieved performance of more than 2.5x current state
of the art, thus enabling stabilization at 4K-UHD resolution.
12.
Vasile, Costin-Emanuel; Bira, Calin; Popescu, George Vladut
TEA/XTEA brute-force cracker for CPU, GPU and FPGA Proceedings Article
In: Brezeanu, G; Buiu, O; Ciurea, ML; Cristea, D; Dinescu, MA; Dobrescu, D; Dragoman, M; Kusko, C; Moldovan, C; Muller, A; Muller, R; Neculoiu, D (Ed.): 2024 INTERNATIONAL SEMICONDUCTOR CONFERENCE, CAS 2024, pp. 249-252, IMT Bucharest, Natl Inst Res & Dev Microtechnologies; Minist Res, Innovat, & Digitalizat Romania; IEEE Electron Devices Soc; IEEE; NANOTEAM; RONEXPRIM; HISTERESIS; SPECS Surface Nano Anal GmbH; Continental Automot Romania SRL; Asociatia Pentru Educatie Antreprenoriala; Carl Zeiss Instruments SRL; AMS 2000 Trading Impex S R L & Rigaku Corp; Schaefer SE Europe srl; RIANA Horizon Europe Project IEEE COMPUTER SOC, 10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1264 USA, 2024, ISSN: 1545-827X, (47th International Semiconductor Conference (CAS), Sinaia, ROMANIA, OCT 09-11, 2024).
Abstract | Links | BibTeX | Tags: TEA; XTEA; brute-force cracker; FPGA; GPU; CPU
@inproceedings{WOS:001361909500053,
title = {TEA/XTEA brute-force cracker for CPU, GPU and FPGA},
author = {Costin-Emanuel Vasile and Calin Bira and George Vladut Popescu},
editor = {G Brezeanu and O Buiu and ML Ciurea and D Cristea and MA Dinescu and D Dobrescu and M Dragoman and C Kusko and C Moldovan and A Muller and R Muller and D Neculoiu},
doi = {10.1109/CAS62834.2024.10736715},
issn = {1545-827X},
year = {2024},
date = {2024-01-01},
booktitle = {2024 INTERNATIONAL SEMICONDUCTOR CONFERENCE, CAS 2024},
pages = {249-252},
publisher = {IEEE COMPUTER SOC},
address = {10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1264 USA},
organization = {IMT Bucharest, Natl Inst Res & Dev Microtechnologies; Minist Res,
Innovat, & Digitalizat Romania; IEEE Electron Devices Soc; IEEE;
NANOTEAM; RONEXPRIM; HISTERESIS; SPECS Surface Nano Anal GmbH;
Continental Automot Romania SRL; Asociatia Pentru Educatie
Antreprenoriala; Carl Zeiss Instruments SRL; AMS 2000 Trading Impex S R
L & Rigaku Corp; Schaefer SE Europe srl; RIANA Horizon Europe Project},
series = {International Semiconductor Conference},
abstract = {This work presents a study comparing Tiny Encryption Algorithm
(TEA/XTEA) brute-force cracker C++ implementations on FPGA, GPU and CPU.
Our HLS FPGA implementation outperformed by at least 2.5x core-per-core
state-of-the art for TEA and 20x for XTEA. For a similar 75W TDP, our
FPGA implementation outperformed our GPU implementation by at least 3x.},
note = {47th International Semiconductor Conference (CAS), Sinaia, ROMANIA, OCT
09-11, 2024},
keywords = {TEA; XTEA; brute-force cracker; FPGA; GPU; CPU},
pubstate = {published},
tppubtype = {inproceedings}
}
This work presents a study comparing Tiny Encryption Algorithm
(TEA/XTEA) brute-force cracker C++ implementations on FPGA, GPU and CPU.
Our HLS FPGA implementation outperformed by at least 2.5x core-per-core
state-of-the art for TEA and 20x for XTEA. For a similar 75W TDP, our
FPGA implementation outperformed our GPU implementation by at least 3x.
(TEA/XTEA) brute-force cracker C++ implementations on FPGA, GPU and CPU.
Our HLS FPGA implementation outperformed by at least 2.5x core-per-core
state-of-the art for TEA and 20x for XTEA. For a similar 75W TDP, our
FPGA implementation outperformed our GPU implementation by at least 3x.
13.
Antonescu, Mihai; Stefan, Gheorghe M.
Multi-Function Scan Circuit for Assisting the Parallel Computational Map Pattern Journal Article
In: ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, vol. 27, no. 1, pp. 1-18, 2024, ISSN: 1453-8245.
Abstract | Links | BibTeX | Tags: Benes network; General-Purpose Accelerator; Multi-Function Permutation circuit; Scan Circuit
@article{WOS:001203088700001,
title = {Multi-Function Scan Circuit for Assisting the Parallel Computational Map
Pattern},
author = {Mihai Antonescu and Gheorghe M. Stefan},
doi = {10.59277/ROMJIST.2024.1.01},
issn = {1453-8245},
year = {2024},
date = {2024-01-01},
journal = {ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY},
volume = {27},
number = {1},
pages = {1-18},
publisher = {EDITURA ACAD ROMANE},
address = {CALEA 13 SEPTEMBRIE NR 13, SECTOR 5, BUCURESTI 050711, ROMANIA},
abstract = {Some parallel computing patterns can be accelerated using appropriate
networks of simple circuits. We propose a solution, based on the
Benes-Waksman permutation network, which is adapted to efficiently
accelerate not only permutation, but some of the most used parallel
computational patterns such as: pack, prefix operations and reductions.
The structural context considered for deploying our circuit is the map
parallel pattern represented by an array of computational elements. The
developed network receives a vector from the map array and outputs a
vector for functions such as permute, pack, prefix sum (thus closing a
first global loop over the map array of cells). For reduction functions
(add, min, max) the network returns a scalar (thus closing a second
global loop over the map array). With these improvements, this network
adds circuit support for frequently used functions, in addition to
map-type functions performed in the array of computing elements. While
for reduction functions the frame of the permutation network can be
easily adapted, for prefix functions and for the pack function new forms
of implementation are proposed. The cells of the Benes-Waksman network
are redesigned to support the additional functionality. Some
applications are then presented to emphasize the utility of our design.},
keywords = {Benes network; General-Purpose Accelerator; Multi-Function Permutation circuit; Scan Circuit},
pubstate = {published},
tppubtype = {article}
}
Some parallel computing patterns can be accelerated using appropriate
networks of simple circuits. We propose a solution, based on the
Benes-Waksman permutation network, which is adapted to efficiently
accelerate not only permutation, but some of the most used parallel
computational patterns such as: pack, prefix operations and reductions.
The structural context considered for deploying our circuit is the map
parallel pattern represented by an array of computational elements. The
developed network receives a vector from the map array and outputs a
vector for functions such as permute, pack, prefix sum (thus closing a
first global loop over the map array of cells). For reduction functions
(add, min, max) the network returns a scalar (thus closing a second
global loop over the map array). With these improvements, this network
adds circuit support for frequently used functions, in addition to
map-type functions performed in the array of computing elements. While
for reduction functions the frame of the permutation network can be
easily adapted, for prefix functions and for the pack function new forms
of implementation are proposed. The cells of the Benes-Waksman network
are redesigned to support the additional functionality. Some
applications are then presented to emphasize the utility of our design.
networks of simple circuits. We propose a solution, based on the
Benes-Waksman permutation network, which is adapted to efficiently
accelerate not only permutation, but some of the most used parallel
computational patterns such as: pack, prefix operations and reductions.
The structural context considered for deploying our circuit is the map
parallel pattern represented by an array of computational elements. The
developed network receives a vector from the map array and outputs a
vector for functions such as permute, pack, prefix sum (thus closing a
first global loop over the map array of cells). For reduction functions
(add, min, max) the network returns a scalar (thus closing a second
global loop over the map array). With these improvements, this network
adds circuit support for frequently used functions, in addition to
map-type functions performed in the array of computing elements. While
for reduction functions the frame of the permutation network can be
easily adapted, for prefix functions and for the pack function new forms
of implementation are proposed. The cells of the Benes-Waksman network
are redesigned to support the additional functionality. Some
applications are then presented to emphasize the utility of our design.
14.
Popescu, Mihai; Zoltan, Hascsi; Srinivasulu, Avireni; Ravariu, Cristian; Doncu, Roxana Elena
Simulation of Logic Circuits using Bursting Neuron Models Proceedings Article
In: Brezeanu, G; Buiu, O; Ciurea, ML; Cristea, D; Dinescu, MA; Dobrescu, D; Dragoman, M; Kusko, C; Moldovan, C; Muller, A; Muller, R; Neculoiu, D (Ed.): 2024 INTERNATIONAL SEMICONDUCTOR CONFERENCE, CAS 2024, pp. 195-198, IMT Bucharest, Natl Inst Res & Dev Microtechnologies; Minist Res, Innovat, & Digitalizat Romania; IEEE Electron Devices Soc; IEEE; NANOTEAM; RONEXPRIM; HISTERESIS; SPECS Surface Nano Anal GmbH; Continental Automot Romania SRL; Asociatia Pentru Educatie Antreprenoriala; Carl Zeiss Instruments SRL; AMS 2000 Trading Impex S R L & Rigaku Corp; Schaefer SE Europe srl; RIANA Horizon Europe Project IEEE COMPUTER SOC, 10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1264 USA, 2024, ISSN: 1545-827X, (47th International Semiconductor Conference (CAS), Sinaia, ROMANIA, OCT 09-11, 2024).
Abstract | Links | BibTeX | Tags: circuit; neuron; logic; gate; pulses train
@inproceedings{WOS:001361909500040,
title = {Simulation of Logic Circuits using Bursting Neuron Models},
author = {Mihai Popescu and Hascsi Zoltan and Avireni Srinivasulu and Cristian Ravariu and Roxana Elena Doncu},
editor = {G Brezeanu and O Buiu and ML Ciurea and D Cristea and MA Dinescu and D Dobrescu and M Dragoman and C Kusko and C Moldovan and A Muller and R Muller and D Neculoiu},
doi = {10.1109/CAS62834.2024.10736729},
issn = {1545-827X},
year = {2024},
date = {2024-01-01},
booktitle = {2024 INTERNATIONAL SEMICONDUCTOR CONFERENCE, CAS 2024},
pages = {195-198},
publisher = {IEEE COMPUTER SOC},
address = {10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1264 USA},
organization = {IMT Bucharest, Natl Inst Res & Dev Microtechnologies; Minist Res,
Innovat, & Digitalizat Romania; IEEE Electron Devices Soc; IEEE;
NANOTEAM; RONEXPRIM; HISTERESIS; SPECS Surface Nano Anal GmbH;
Continental Automot Romania SRL; Asociatia Pentru Educatie
Antreprenoriala; Carl Zeiss Instruments SRL; AMS 2000 Trading Impex S R
L & Rigaku Corp; Schaefer SE Europe srl; RIANA Horizon Europe Project},
series = {International Semiconductor Conference},
abstract = {A neuron can be perceived as analog circuit in terms of voltage-time
characteristics. Sometimes, at function level, it can be rather
considered a logic circuit. This later approach is not so indefensible
because the neuron membrane always works between two voltage levels,
immediately associated by a binary logic. These levels are changing at a
certain group of pulses on its exciting or inhibiting input synapses.
Being hard to describe exactly the neural calculus processes inside the
human brain we create some models able to mimic these processes. In this
paper we proposed some neuronal models able to implement logic gates.
The envelope signal shelters the pulses train that stimulate any neuron,
and this envelope signal ensure the digital function, as a main element
of originality.},
note = {47th International Semiconductor Conference (CAS), Sinaia, ROMANIA, OCT
09-11, 2024},
keywords = {circuit; neuron; logic; gate; pulses train},
pubstate = {published},
tppubtype = {inproceedings}
}
A neuron can be perceived as analog circuit in terms of voltage-time
characteristics. Sometimes, at function level, it can be rather
considered a logic circuit. This later approach is not so indefensible
because the neuron membrane always works between two voltage levels,
immediately associated by a binary logic. These levels are changing at a
certain group of pulses on its exciting or inhibiting input synapses.
Being hard to describe exactly the neural calculus processes inside the
human brain we create some models able to mimic these processes. In this
paper we proposed some neuronal models able to implement logic gates.
The envelope signal shelters the pulses train that stimulate any neuron,
and this envelope signal ensure the digital function, as a main element
of originality.
characteristics. Sometimes, at function level, it can be rather
considered a logic circuit. This later approach is not so indefensible
because the neuron membrane always works between two voltage levels,
immediately associated by a binary logic. These levels are changing at a
certain group of pulses on its exciting or inhibiting input synapses.
Being hard to describe exactly the neural calculus processes inside the
human brain we create some models able to mimic these processes. In this
paper we proposed some neuronal models able to implement logic gates.
The envelope signal shelters the pulses train that stimulate any neuron,
and this envelope signal ensure the digital function, as a main element
of originality.
15.
Pietricică, Andreea-Cătălina; Antonescu, Mihai; Popescu, George-Vlăduț
Evaluation of AES Cryptographic Algorithm on a General-Purpose Map-Scan Accelerator Proceedings Article
In: 2023 International Semiconductor Conference (CAS), pp. 99-102, 2023, ISSN: 2377-0678.
Abstract | Links | BibTeX | Tags: Couplings;Microprocessors;Computer architecture;Parallel processing;Throughput;Hardware;Encryption;AES;ECB;CTR;Heterogeneous computing system;Map-Reduce;Map-Scan;Accelerator
@inproceedings{10303705,
title = {Evaluation of AES Cryptographic Algorithm on a General-Purpose Map-Scan Accelerator},
author = {Andreea-Cătălina Pietricică and Mihai Antonescu and George-Vlăduț Popescu},
doi = {10.1109/CAS59036.2023.10303705},
issn = {2377-0678},
year = {2023},
date = {2023-10-01},
booktitle = {2023 International Semiconductor Conference (CAS)},
pages = {99-102},
abstract = {As one of the most widely used encryption standards, AES must be implemented taking encryption speed into consideration. This paper presents the evaluation of the AES algorithm on a general-purpose Map-Scan Accelerator. AES proves well suited to a Map style of parallelism, with each computational cell processing one block of data. ECB and CTR modes are implemented and evaluated for key sizes of 128, 192, and 256.},
keywords = {Couplings;Microprocessors;Computer architecture;Parallel processing;Throughput;Hardware;Encryption;AES;ECB;CTR;Heterogeneous computing system;Map-Reduce;Map-Scan;Accelerator},
pubstate = {published},
tppubtype = {inproceedings}
}
As one of the most widely used encryption standards, AES must be implemented taking encryption speed into consideration. This paper presents the evaluation of the AES algorithm on a general-purpose Map-Scan Accelerator. AES proves well suited to a Map style of parallelism, with each computational cell processing one block of data. ECB and CTR modes are implemented and evaluated for key sizes of 128, 192, and 256.
16.
Antonescu, Mihai; Maliţa, Mihaela; Ştefan, Gheorghe M.
Latency Hiding of Log-Depth Scan and Reduce Networks in Heterogenous Embedded Systems Proceedings Article
In: 2023 IEEE 29th International Symposium for Design and Technology in Electronic Packaging (SIITME), pp. 81-86, 2023, ISSN: 2642-7036.
Abstract | Links | BibTeX | Tags: Program processors;Embedded systems;Power demand;Electron accelerators;Computer architecture;Pipeline processing;Electronics packaging;Latency avoidance;Map-Scan accelerator;MapReduce accelerator
@inproceedings{10430611,
title = {Latency Hiding of Log-Depth Scan and Reduce Networks in Heterogenous Embedded Systems},
author = {Mihai Antonescu and Mihaela Maliţa and Gheorghe M. Ştefan},
doi = {10.1109/SIITME59799.2023.10430611},
issn = {2642-7036},
year = {2023},
date = {2023-10-01},
booktitle = {2023 IEEE 29th International Symposium for Design and Technology in Electronic Packaging (SIITME)},
pages = {81-86},
abstract = {This paper discusses methods, algorithmic examples and general principles regarding latency reduction methods for single chip Map-Reduce and Map-Scan many-core architectures. Processors designed for embedded systems suffer performance limitations (both performance and power consumption) when running intense instead of complex computations. A common solution is to add accelerators to the host processor in order to offload parts of the intense computations. We consider a Map-Scan-Reduce many-core architecture to be highly effective as a general-purpose accelerator and in this paper, we discuss the latencies introduced by the Scan and Reduce networks and ways in which to hide them based on practical applications and the solutions we have employed. Proper usage of pipelining technique and algorithmic improvements helps us obtain in simulations supralinear accelerations in relation to the number of processing cores used for the algorithms presented: matrixvector/matrix multiplication, FFT, pooling.},
keywords = {Program processors;Embedded systems;Power demand;Electron accelerators;Computer architecture;Pipeline processing;Electronics packaging;Latency avoidance;Map-Scan accelerator;MapReduce accelerator},
pubstate = {published},
tppubtype = {inproceedings}
}
This paper discusses methods, algorithmic examples and general principles regarding latency reduction methods for single chip Map-Reduce and Map-Scan many-core architectures. Processors designed for embedded systems suffer performance limitations (both performance and power consumption) when running intense instead of complex computations. A common solution is to add accelerators to the host processor in order to offload parts of the intense computations. We consider a Map-Scan-Reduce many-core architecture to be highly effective as a general-purpose accelerator and in this paper, we discuss the latencies introduced by the Scan and Reduce networks and ways in which to hide them based on practical applications and the solutions we have employed. Proper usage of pipelining technique and algorithmic improvements helps us obtain in simulations supralinear accelerations in relation to the number of processing cores used for the algorithms presented: matrixvector/matrix multiplication, FFT, pooling.
17.
Bira, Calin; Ionescu, Liviu; Rusu-Casandra, Alexandru
The Radar Signal Processor of the First Romanian Space Surveillance Radar Journal Article
In: REMOTE SENSING, vol. 15, no. 14, 2023.
Abstract | Links | BibTeX | Tags: radar; space debris; space situation awareness; low Earth orbit; digital signal processing
@article{WOS:001069861300001,
title = {The Radar Signal Processor of the First Romanian Space Surveillance
Radar},
author = {Calin Bira and Liviu Ionescu and Alexandru Rusu-Casandra},
doi = {10.3390/rs15143630},
year = {2023},
date = {2023-07-01},
journal = {REMOTE SENSING},
volume = {15},
number = {14},
publisher = {MDPI},
address = {MDPI AG, Grosspeteranlage 5, CH-4052 BASEL, SWITZERLAND},
abstract = {This paper describes the work for the radar signal processor, the core
of the Cheia space surveillance radar. It presents the basic operation,
the requirements and the achieved processing performance together with a
description of optimizations both in terms of signal-to-noise ratio and
in terms of software processing. The Cheia Radar is financed by the
European Space Agency and will be used for the tracking of low Earth
orbit objects and for refining the international catalogs of space
objects.},
keywords = {radar; space debris; space situation awareness; low Earth orbit; digital signal processing},
pubstate = {published},
tppubtype = {article}
}
This paper describes the work for the radar signal processor, the core
of the Cheia space surveillance radar. It presents the basic operation,
the requirements and the achieved processing performance together with a
description of optimizations both in terms of signal-to-noise ratio and
in terms of software processing. The Cheia Radar is financed by the
European Space Agency and will be used for the tracking of low Earth
orbit objects and for refining the international catalogs of space
objects.
of the Cheia space surveillance radar. It presents the basic operation,
the requirements and the achieved processing performance together with a
description of optimizations both in terms of signal-to-noise ratio and
in terms of software processing. The Cheia Radar is financed by the
European Space Agency and will be used for the tracking of low Earth
orbit objects and for refining the international catalogs of space
objects.
18.
Antonescu, Mihai; Maliţa, Mihaela; Ştefan, Gheorghe M.
Avoiding Latencies of Log-Depth Parallel Computational Patterns Proceedings Article
In: 2023 22nd International Symposium on Parallel and Distributed Computing (ISPDC), pp. 116-116, 2023, ISSN: 2379-5352.
Abstract | Links | BibTeX | Tags: Parallel processing;Complexity theory;Distributed computing;parallel circuits;reduce network;scan network;latency reduction
@inproceedings{10272423,
title = {Avoiding Latencies of Log-Depth Parallel Computational Patterns},
author = {Mihai Antonescu and Mihaela Maliţa and Gheorghe M. Ştefan},
doi = {10.1109/ISPDC59212.2023.00009},
issn = {2379-5352},
year = {2023},
date = {2023-07-01},
booktitle = {2023 22nd International Symposium on Parallel and Distributed Computing (ISPDC)},
pages = {116-116},
abstract = {Above a certain level of complexity, effects appear that reduce the performance of a parallel system. In the context of one-chip parallel computing systems, common parallel patterns can sometimes be expressed as circuits. These circuits introduce latency which heavily reduces speed performance.},
keywords = {Parallel processing;Complexity theory;Distributed computing;parallel circuits;reduce network;scan network;latency reduction},
pubstate = {published},
tppubtype = {inproceedings}
}
Above a certain level of complexity, effects appear that reduce the performance of a parallel system. In the context of one-chip parallel computing systems, common parallel patterns can sometimes be expressed as circuits. These circuits introduce latency which heavily reduces speed performance.
19.
Dediu, Marius; Vasile, Costin-Emanuel; Bira, Calin
Deep Layer Aggregation Architectures for Photorealistic Universal Style Transfer Journal Article
In: SENSORS, vol. 23, no. 9, 2023.
Abstract | Links | BibTeX | Tags: deep learning; photorealistic; style transfer; deep layer aggregation
@article{WOS:000988076400001,
title = {Deep Layer Aggregation Architectures for Photorealistic Universal Style
Transfer},
author = {Marius Dediu and Costin-Emanuel Vasile and Calin Bira},
doi = {10.3390/s23094528},
year = {2023},
date = {2023-05-01},
journal = {SENSORS},
volume = {23},
number = {9},
publisher = {MDPI},
address = {ST ALBAN-ANLAGE 66, CH-4052 BASEL, SWITZERLAND},
abstract = {This paper introduces a deep learning approach to photorealistic
universal style transfer that extends the PhotoNet network architecture
by adding extra feature-aggregation modules. Given a pair of images
representing the content and the reference of style, we augment the
state-of-the-art solution mentioned above with deeper aggregation, to
better fuse content and style information across the decoding layers. As
opposed to the more flexible implementation of PhotoNet (i.e.,
PhotoNAS), which targets the minimization of inference time, our method
aims to achieve better image reconstruction and a more pleasant
stylization. We propose several deep layer aggregation architectures to
be used as wrappers over PhotoNet, to enhance the stylization and
quality of the output image.},
keywords = {deep learning; photorealistic; style transfer; deep layer aggregation},
pubstate = {published},
tppubtype = {article}
}
This paper introduces a deep learning approach to photorealistic
universal style transfer that extends the PhotoNet network architecture
by adding extra feature-aggregation modules. Given a pair of images
representing the content and the reference of style, we augment the
state-of-the-art solution mentioned above with deeper aggregation, to
better fuse content and style information across the decoding layers. As
opposed to the more flexible implementation of PhotoNet (i.e.,
PhotoNAS), which targets the minimization of inference time, our method
aims to achieve better image reconstruction and a more pleasant
stylization. We propose several deep layer aggregation architectures to
be used as wrappers over PhotoNet, to enhance the stylization and
quality of the output image.
universal style transfer that extends the PhotoNet network architecture
by adding extra feature-aggregation modules. Given a pair of images
representing the content and the reference of style, we augment the
state-of-the-art solution mentioned above with deeper aggregation, to
better fuse content and style information across the decoding layers. As
opposed to the more flexible implementation of PhotoNet (i.e.,
PhotoNAS), which targets the minimization of inference time, our method
aims to achieve better image reconstruction and a more pleasant
stylization. We propose several deep layer aggregation architectures to
be used as wrappers over PhotoNet, to enhance the stylization and
quality of the output image.
20.
Stefan, Gheorghe M.
Meaning in Action: a Qualitative Approach of Information Journal Article
In: ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, vol. 26, no. 3-4, pp. 289-300, 2023, ISSN: 1453-8245.
Abstract | Links | BibTeX | Tags:
@article{WOS:001083522800003,
title = {Meaning in Action: a Qualitative Approach of Information},
author = {Gheorghe M. Stefan},
doi = {10.59277/ROMJIST.2023.3-4.03},
issn = {1453-8245},
year = {2023},
date = {2023-01-01},
journal = {ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY},
volume = {26},
number = {3-4},
pages = {289-300},
publisher = {EDITURA ACAD ROMANE},
address = {CALEA 13 SEPTEMBRIE NR 13, SECTOR 5, BUCURESTI 050711, ROMANIA},
abstract = {There are many approaches to the concept of information in terms of
quantity, but there is a lack of consensus on what information is. We
measure it in many ways, but we don't consistently state what
information is. We will try in this text to offer a qualitative image
for the concept of information. On this occasion, perhaps we will better
understand the role of information at different levels in existence by
defining information as a symbolic structure that acts through the
meaning it has in a given context.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
There are many approaches to the concept of information in terms of
quantity, but there is a lack of consensus on what information is. We
measure it in many ways, but we don't consistently state what
information is. We will try in this text to offer a qualitative image
for the concept of information. On this occasion, perhaps we will better
understand the role of information at different levels in existence by
defining information as a symbolic structure that acts through the
meaning it has in a given context.
quantity, but there is a lack of consensus on what information is. We
measure it in many ways, but we don't consistently state what
information is. We will try in this text to offer a qualitative image
for the concept of information. On this occasion, perhaps we will better
understand the role of information at different levels in existence by
defining information as a symbolic structure that acts through the
meaning it has in a given context.