1.
Vasile, Costin-Emanuel; Ulmamei, Andrei-Alexandru; Bira, Calin
Image Processing Hardware Acceleration-A Review of Operations Involved and Current Hardware Approaches Journal Article
In: JOURNAL OF IMAGING, vol. 10, no. 12, 2024.
Abstract | Links | BibTeX | Tags: image processing; neural networks; hardware accelerators; FPGA
@article{WOS:001386823200001,
title = {Image Processing Hardware Acceleration-A Review of Operations Involved
and Current Hardware Approaches},
author = {Costin-Emanuel Vasile and Andrei-Alexandru Ulmamei and Calin Bira},
doi = {10.3390/jimaging10120298},
year = {2024},
date = {2024-12-01},
journal = {JOURNAL OF IMAGING},
volume = {10},
number = {12},
publisher = {MDPI},
address = {MDPI AG, Grosspeteranlage 5, CH-4052 BASEL, SWITZERLAND},
abstract = {This review provides an in-depth analysis of current hardware
acceleration approaches for image processing and neural network
inference, focusing on key operations involved in these applications and
the hardware platforms used to deploy them. We examine various
solutions, including traditional CPU-GPU systems, custom ASIC designs,
and FPGA implementations, while also considering emerging low-power,
resource-constrained devices.},
keywords = {image processing; neural networks; hardware accelerators; FPGA},
pubstate = {published},
tppubtype = {article}
}
This review provides an in-depth analysis of current hardware
acceleration approaches for image processing and neural network
inference, focusing on key operations involved in these applications and
the hardware platforms used to deploy them. We examine various
solutions, including traditional CPU-GPU systems, custom ASIC designs,
and FPGA implementations, while also considering emerging low-power,
resource-constrained devices.
acceleration approaches for image processing and neural network
inference, focusing on key operations involved in these applications and
the hardware platforms used to deploy them. We examine various
solutions, including traditional CPU-GPU systems, custom ASIC designs,
and FPGA implementations, while also considering emerging low-power,
resource-constrained devices.