1.
Vasile, Costin-Emanuel; Bîră, Călin; Popescu, George-Vlădut
XTEA Brute-Force Cracker for FPGA in HLS and HDL Proceedings Article
In: 2024 International Symposium on Electronics and Telecommunications (ISETC), pp. 1-4, 2024, ISSN: 2475-7861.
Abstract | Links | BibTeX | Tags: Graphics processing units;Companies;C++ languages;Benchmark testing;Encryption;Telecommunications;Power dissipation;Hardware design languages;Field programmable gate arrays;XTEA;brute-force cracker;FPGA;HLS;HDL
@inproceedings{10797331,
title = {XTEA Brute-Force Cracker for FPGA in HLS and HDL},
author = {Costin-Emanuel Vasile and Călin Bîră and George-Vlădut Popescu},
doi = {10.1109/ISETC63109.2024.10797331},
issn = {2475-7861},
year = {2024},
date = {2024-11-01},
booktitle = {2024 International Symposium on Electronics and Telecommunications (ISETC)},
pages = {1-4},
abstract = {This work presents a study comparing Extended Tiny Encryption Algorithm (XTEA) brute-force cracker C++/hlsand Verilog/HDL implementations on FPGA. The HDL-based implementation outperformed the HLS-based implementation by a factor of 2.8, and it also demonstrated exceptionally low total power dissipation compared to both CPU and GPU implementations.},
keywords = {Graphics processing units;Companies;C++ languages;Benchmark testing;Encryption;Telecommunications;Power dissipation;Hardware design languages;Field programmable gate arrays;XTEA;brute-force cracker;FPGA;HLS;HDL},
pubstate = {published},
tppubtype = {inproceedings}
}
This work presents a study comparing Extended Tiny Encryption Algorithm (XTEA) brute-force cracker C++/hlsand Verilog/HDL implementations on FPGA. The HDL-based implementation outperformed the HLS-based implementation by a factor of 2.8, and it also demonstrated exceptionally low total power dissipation compared to both CPU and GPU implementations.