1.
Antonescu, Mihai; Maliţa, Mihaela; Ştefan, Gheorghe M.
Avoiding Latencies of Log-Depth Parallel Computational Patterns Proceedings Article
In: 2023 22nd International Symposium on Parallel and Distributed Computing (ISPDC), pp. 116-116, 2023, ISSN: 2379-5352.
Abstract | Links | BibTeX | Tags: Parallel processing;Complexity theory;Distributed computing;parallel circuits;reduce network;scan network;latency reduction
@inproceedings{10272423,
title = {Avoiding Latencies of Log-Depth Parallel Computational Patterns},
author = {Mihai Antonescu and Mihaela Maliţa and Gheorghe M. Ştefan},
doi = {10.1109/ISPDC59212.2023.00009},
issn = {2379-5352},
year = {2023},
date = {2023-07-01},
booktitle = {2023 22nd International Symposium on Parallel and Distributed Computing (ISPDC)},
pages = {116-116},
abstract = {Above a certain level of complexity, effects appear that reduce the performance of a parallel system. In the context of one-chip parallel computing systems, common parallel patterns can sometimes be expressed as circuits. These circuits introduce latency which heavily reduces speed performance.},
keywords = {Parallel processing;Complexity theory;Distributed computing;parallel circuits;reduce network;scan network;latency reduction},
pubstate = {published},
tppubtype = {inproceedings}
}
Above a certain level of complexity, effects appear that reduce the performance of a parallel system. In the context of one-chip parallel computing systems, common parallel patterns can sometimes be expressed as circuits. These circuits introduce latency which heavily reduces speed performance.