1.
Malita, Mihaela; Popescu, George Vladut; Stefan, Gheorghe M.
Pseudo-Reconfigurable Heterogeneous Solution for Accelerating Spectral Clustering Proceedings Article
In: Wu, XT; Jermaine, C; Xiong, L; Hu, XH; Kotevska, O; Lu, SY; Xu, WJ; Aluru, S; Zhai, CX; Al-Masri, E; Chen, ZY; Saltz, J (Ed.): 2020 IEEE INTERNATIONAL CONFERENCE ON BIG DATA (BIG DATA), pp. 5138-5145, IEEE; IEEE Comp Soc; IBM; Ankura IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2020, ISSN: 2639-1589, (8th IEEE International Conference on Big Data (Big Data), ELECTR NETWORK, DEC 10-13, 2020).
Abstract | Links | BibTeX | Tags: Spectral clustering; parallel algorithm; parallel computing; accelerator; heterogeneous computing; pseudo-reconfigurable computing
@inproceedings{WOS:000662554705026,
title = {Pseudo-Reconfigurable Heterogeneous Solution for Accelerating Spectral
Clustering},
author = {Mihaela Malita and George Vladut Popescu and Gheorghe M. Stefan},
editor = {XT Wu and C Jermaine and L Xiong and XH Hu and O Kotevska and SY Lu and WJ Xu and S Aluru and CX Zhai and E Al-Masri and ZY Chen and J Saltz},
doi = {10.1109/BigData50022.2020.9378150},
issn = {2639-1589},
year = {2020},
date = {2020-01-01},
booktitle = {2020 IEEE INTERNATIONAL CONFERENCE ON BIG DATA (BIG DATA)},
pages = {5138-5145},
publisher = {IEEE},
address = {345 E 47TH ST, NEW YORK, NY 10017 USA},
organization = {IEEE; IEEE Comp Soc; IBM; Ankura},
series = {IEEE International Conference on Big Data},
abstract = {Spectral clustering is a Machine Learning technique intensively used in
Big Data applications. It makes extensive use of linear algebra. This
article introduces the concept of MapReduce Accelerator (MRA) as the
reconfigurable part of a heterogeneous computing system. Although the
accelerator we propose is a general purpose one, it has some specific
features related to the targeted application. This is possible due to
the pseudo-reconfigurable environment which deploys in FPGA a
parameterizable programmable accelerator. The main specific
characteristics of the accelerator are proposed as a result of the
analysis performed on the spectral clustering algorithms. The
architecture is described and the spectral clustering algorithms are
evaluated. The proposed solution is compared, in terms of computing
performance and energy consumption, with other solutions published in
the literature. The increase in computing performance is accompanied by
a 3-5 times reduction in energy consumed. The accelerator is a linear
array of cells controlled by a sequencer loop closed through a reduction
network. Each cell is a simple, accumulator-based execution unit with a
big two-port register file. The reduction network is a log-depth
pipelined circuit performing few reduction functions such as add, min,
max. The experimental system is a PYNQ-Z2 board equipped with Zinq 7020
SoC; it is used to implement and evaluate the acceleration provided by
an 128-cell MRA.},
note = {8th IEEE International Conference on Big Data (Big Data), ELECTR
NETWORK, DEC 10-13, 2020},
keywords = {Spectral clustering; parallel algorithm; parallel computing; accelerator; heterogeneous computing; pseudo-reconfigurable computing},
pubstate = {published},
tppubtype = {inproceedings}
}
Spectral clustering is a Machine Learning technique intensively used in
Big Data applications. It makes extensive use of linear algebra. This
article introduces the concept of MapReduce Accelerator (MRA) as the
reconfigurable part of a heterogeneous computing system. Although the
accelerator we propose is a general purpose one, it has some specific
features related to the targeted application. This is possible due to
the pseudo-reconfigurable environment which deploys in FPGA a
parameterizable programmable accelerator. The main specific
characteristics of the accelerator are proposed as a result of the
analysis performed on the spectral clustering algorithms. The
architecture is described and the spectral clustering algorithms are
evaluated. The proposed solution is compared, in terms of computing
performance and energy consumption, with other solutions published in
the literature. The increase in computing performance is accompanied by
a 3-5 times reduction in energy consumed. The accelerator is a linear
array of cells controlled by a sequencer loop closed through a reduction
network. Each cell is a simple, accumulator-based execution unit with a
big two-port register file. The reduction network is a log-depth
pipelined circuit performing few reduction functions such as add, min,
max. The experimental system is a PYNQ-Z2 board equipped with Zinq 7020
SoC; it is used to implement and evaluate the acceleration provided by
an 128-cell MRA.
Big Data applications. It makes extensive use of linear algebra. This
article introduces the concept of MapReduce Accelerator (MRA) as the
reconfigurable part of a heterogeneous computing system. Although the
accelerator we propose is a general purpose one, it has some specific
features related to the targeted application. This is possible due to
the pseudo-reconfigurable environment which deploys in FPGA a
parameterizable programmable accelerator. The main specific
characteristics of the accelerator are proposed as a result of the
analysis performed on the spectral clustering algorithms. The
architecture is described and the spectral clustering algorithms are
evaluated. The proposed solution is compared, in terms of computing
performance and energy consumption, with other solutions published in
the literature. The increase in computing performance is accompanied by
a 3-5 times reduction in energy consumed. The accelerator is a linear
array of cells controlled by a sequencer loop closed through a reduction
network. Each cell is a simple, accumulator-based execution unit with a
big two-port register file. The reduction network is a log-depth
pipelined circuit performing few reduction functions such as add, min,
max. The experimental system is a PYNQ-Z2 board equipped with Zinq 7020
SoC; it is used to implement and evaluate the acceleration provided by
an 128-cell MRA.