@inproceedings{WOS:000637264600028,
title = {Multi-Function Scan Circuit},
author = {Mihai Antonescu and Gheorghe M. Stefan},
editor = {I Stavarache and G Stefan and T Stoica and A Takacs and A Tulbure and ML Veca and T Visan and RC Voicu and G Brezeanu and ML Ciurea and D Cristea and MA Dinescu and D Dobrescu and M Dragoman and A Muller and R Muller and D Neculoiu},
doi = {10.1109/cas50358.2020.9268048},
issn = {1545-827X},
year = {2020},
date = {2020-01-01},
booktitle = {CAS 2020 PROCEEDINGS: 2020 INTERNATIONAL SEMICONDUCTOR CONFERENCE},
pages = {123-126},
publisher = {IEEE},
address = {345 E 47TH ST, NEW YORK, NY 10017 USA},
organization = {Natl Inst Res & Dev Microtehnologies IMT Bucharest; IEEE Electron
Devices Soc; Minist Educ & Res; Guvernul Romaniei},
series = {International Semiconductor Conference},
abstract = {The practice of parallel computing emphasizes frequently used patterns.
Some of them can be accelerated using appropriate networks of simple
circuits. We propose a solution, based on the frame offered by the Benes
permutation network. It is adapted to efficiently accelerate some of the
most used parallel computation patterns: prefix, split, reduction. The
cells of the Benes network associated to a Map pattern of n units are
designed to support the additional functions. Two versions are
considered: a log-depth pipelined version and a sequential, iterative
version.},
note = {43rd International Semiconductor Conference (CAS), ELECTR NETWORK, OCT
07-09, 2020},
keywords = {scan; reduction; prefix; permute; split},
pubstate = {published},
tppubtype = {inproceedings}
}
