Publications

@article{WOS:000503865200012,

title = {ALL-PAIR SHORTEST PATH ON A HYBRID MAP-REDUCE BASED ARCHITECTURE},

author = {Voichita Dragomir and Gheorghe M. Stefan},

issn = {1454-9069},

year  = {2019},

date = {2019-10-01},

journal = {PROCEEDINGS OF THE ROMANIAN ACADEMY SERIES A-MATHEMATICS PHYSICS 

 TECHNICAL SCIENCES INFORMATION SCIENCE},

volume = {20},

number = {4},

pages = {409-415},

publisher = {EDITURA ACAD ROMANE},

address = {CALEA 13 SEPTEMBRIE NR 13, SECTOR 5, BUCURESTI 050711, ROMANIA},

abstract = {All-Path Shortest-Path Problem (APSP) algorithm implemented on two 

 currently used architectures, a mono-core one and on a many-core one, is 

 compared with the implementation on Map-Reduce Architecture (MRA), a 

 novel many-core architecture we propose. The hybrid system using an 

 accelerator based on MRA is described. The system is evaluated in two 

 versions for miming the Floyd-Warshall APSP algorithm. A first version 

 is for an accelerator with the number of cores, p, exceeding the number 

 of vertexes, vertical bar V vertical bar, while the second uses a fix number of cells, N, vertical bar V vertical bar for = NxM, where M is a 

 power of 2. The programs, written for our accelerator running in 

 simulation, are used to evaluate the execution time for both versions. 

 The performance of a mono-core and of a GPU is compared with our MRA 

 acceleration. A 128-cell MRA engine accelerates 118x at 20 x less energy 

 a mono-core, and 3x at 26 x less energy a 128-core GPU.},

keywords = {APSP; parallelism; hybrid computation; map-reduce architecture;   Floyd-Warshall algorithm},

pubstate = {published},

tppubtype = {article}

}