1.
Dinu, Alexandru; Gheorghe, Stefan; Danciu, Gabriel Mihail; Ogrutan, Petre Lucian
Debugging FPGA projects using artificial intelligence Journal Article
In: ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, vol. 24, no. 3, pp. 299-320, 2021, ISSN: 1453-8245.
Abstract | BibTeX | Tags: data mining and analysis; FPGA; machine learning; deep learning; reference model; neural network configuration
@article{WOS:000704174600003,
title = {Debugging FPGA projects using artificial intelligence},
author = {Alexandru Dinu and Stefan Gheorghe and Gabriel Mihail Danciu and Petre Lucian Ogrutan},
issn = {1453-8245},
year = {2021},
date = {2021-01-01},
journal = {ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY},
volume = {24},
number = {3},
pages = {299-320},
publisher = {EDITURA ACAD ROMANE},
address = {CALEA 13 SEPTEMBRIE NR 13, SECTOR 5, BUCURESTI 050711, ROMANIA},
abstract = {Debugging digital designs implemented into FPGA devices is a challenging
task. As opposite to simulation, simultaneous access to all input and
output signals is not possible. The main obstacles in the debugging
process are a limited number of input/output ports of FPGAs and the
transfer of information from a digital device to an external data
processor. However, debugging a digital design requests analysis of many
combinations of inputs and outputs of a module to assess if these are
well correlated and if their operation matches device specifications.
The current work of the research team consisted of designing an
end-to-end flow of data processing that fulfills the aim of debugging
digital designs (particularly in this work, FPGA devices are
considered). Firstly, a data generator based on majority voting idea was
created using RTL languages. After checking its behavior using
simulation, it has been downloaded into the FPGA fabric of a Spartan 3E
board. The data generated from this reconfigurable device was acquired
through the UART protocol, using an FT232R adapter. It was preprocessed
to reconstruct the fields of each data sample and to remove transmission
errors. The team analyzed the distribution of the obtained values and
adjusted the data to achieve a uniform distribution. The team used the
data to train both machine learning and deep learning models to create a
golden reference model which accurately reflects the main functionality
of the DUT: executing the majority vote operation over three pairs of
numbers. Finally, the team presented how to use the resulting reference
model to debug digital systems.},
keywords = {data mining and analysis; FPGA; machine learning; deep learning; reference model; neural network configuration},
pubstate = {published},
tppubtype = {article}
}
Debugging digital designs implemented into FPGA devices is a challenging
task. As opposite to simulation, simultaneous access to all input and
output signals is not possible. The main obstacles in the debugging
process are a limited number of input/output ports of FPGAs and the
transfer of information from a digital device to an external data
processor. However, debugging a digital design requests analysis of many
combinations of inputs and outputs of a module to assess if these are
well correlated and if their operation matches device specifications.
The current work of the research team consisted of designing an
end-to-end flow of data processing that fulfills the aim of debugging
digital designs (particularly in this work, FPGA devices are
considered). Firstly, a data generator based on majority voting idea was
created using RTL languages. After checking its behavior using
simulation, it has been downloaded into the FPGA fabric of a Spartan 3E
board. The data generated from this reconfigurable device was acquired
through the UART protocol, using an FT232R adapter. It was preprocessed
to reconstruct the fields of each data sample and to remove transmission
errors. The team analyzed the distribution of the obtained values and
adjusted the data to achieve a uniform distribution. The team used the
data to train both machine learning and deep learning models to create a
golden reference model which accurately reflects the main functionality
of the DUT: executing the majority vote operation over three pairs of
numbers. Finally, the team presented how to use the resulting reference
model to debug digital systems.
task. As opposite to simulation, simultaneous access to all input and
output signals is not possible. The main obstacles in the debugging
process are a limited number of input/output ports of FPGAs and the
transfer of information from a digital device to an external data
processor. However, debugging a digital design requests analysis of many
combinations of inputs and outputs of a module to assess if these are
well correlated and if their operation matches device specifications.
The current work of the research team consisted of designing an
end-to-end flow of data processing that fulfills the aim of debugging
digital designs (particularly in this work, FPGA devices are
considered). Firstly, a data generator based on majority voting idea was
created using RTL languages. After checking its behavior using
simulation, it has been downloaded into the FPGA fabric of a Spartan 3E
board. The data generated from this reconfigurable device was acquired
through the UART protocol, using an FT232R adapter. It was preprocessed
to reconstruct the fields of each data sample and to remove transmission
errors. The team analyzed the distribution of the obtained values and
adjusted the data to achieve a uniform distribution. The team used the
data to train both machine learning and deep learning models to create a
golden reference model which accurately reflects the main functionality
of the DUT: executing the majority vote operation over three pairs of
numbers. Finally, the team presented how to use the resulting reference
model to debug digital systems.