1.
Stefan, G.; Draghici, F.
Memory management unit-a new principle for LRU implementation Proceedings Article
In: [1991 Proceedings] 6th Mediterranean Electrotechnical Conference, pp. 989-992 vol.2, 1991.
Abstract | Links | BibTeX | Tags: Memory management;Clocks;Automatic control;Cache memory;Strontium;Shift registers;Logic circuits
@inproceedings{162008,
title = {Memory management unit-a new principle for LRU implementation},
author = {G. Stefan and F. Draghici},
doi = {10.1109/MELCON.1991.162008},
year = {1991},
date = {1991-05-01},
booktitle = {[1991 Proceedings] 6th Mediterranean Electrotechnical Conference},
pages = {989-992 vol.2},
abstract = {A new principle is presented for a memory management unit (MMU) which contains a new circuit for LRU (least recently used) implementation. A MMU has been chosen for study. It works with a 24-b address processor for which it facilitates access to a virtual memory (VM) of 16 Mwords, available on a disk, through the assistance of a paginated dynamic primary memory (PM) of 1 Mword, which keeps the most recently used (MRU) pages.<>},
keywords = {Memory management;Clocks;Automatic control;Cache memory;Strontium;Shift registers;Logic circuits},
pubstate = {published},
tppubtype = {inproceedings}
}
A new principle is presented for a memory management unit (MMU) which contains a new circuit for LRU (least recently used) implementation. A MMU has been chosen for study. It works with a 24-b address processor for which it facilitates access to a virtual memory (VM) of 16 Mwords, available on a disk, through the assistance of a paginated dynamic primary memory (PM) of 1 Mword, which keeps the most recently used (MRU) pages.<>