1.
Antonescu, Mihai; Ștefan, Gheorghe M.
Multi-Function Scan Circuit Proceedings Article
In: 2020 International Semiconductor Conference (CAS), pp. 123-126, 2020, ISSN: 2377-0678.
Abstract | Links | BibTeX | Tags: Registers;Acceleration;Switches;Shape;Process control;Pipelines;Multiplexing;scan;reduction;prefix;permute;split
@inproceedings{9268048,
title = {Multi-Function Scan Circuit},
author = {Mihai Antonescu and Gheorghe M. Ștefan},
doi = {10.1109/CAS50358.2020.9268048},
issn = {2377-0678},
year = {2020},
date = {2020-10-01},
booktitle = {2020 International Semiconductor Conference (CAS)},
pages = {123-126},
abstract = {The practice of parallel computing emphasizes frequently used patterns. Some of them can be accelerated using appropriate networks of simple circuits. We propose a solution, based on the frame offered by the Beneš permutation network. It is adapted to efficiently accelerate some of the most used parallel computation patterns: prefix, split, reduction. The cells of the Beneš network associated to a Map pattern of n units are designed to support the additional functions. Two versions are considered: a log-depth pipelined version and a sequential, iterative version.},
keywords = {Registers;Acceleration;Switches;Shape;Process control;Pipelines;Multiplexing;scan;reduction;prefix;permute;split},
pubstate = {published},
tppubtype = {inproceedings}
}
The practice of parallel computing emphasizes frequently used patterns. Some of them can be accelerated using appropriate networks of simple circuits. We propose a solution, based on the frame offered by the Beneš permutation network. It is adapted to efficiently accelerate some of the most used parallel computation patterns: prefix, split, reduction. The cells of the Beneš network associated to a Map pattern of n units are designed to support the additional functions. Two versions are considered: a log-depth pipelined version and a sequential, iterative version.