1.
Hobincu, Radu; Datcu, Octaviana
FPGA Implementation of a Chaos Based PRNG Targetting Secret Communication Proceedings Article
In: 2018 International Symposium on Electronics and Telecommunications (ISETC), pp. 1-4, 2018, ISSN: 2475-7861.
Abstract | Links | BibTeX | Tags: Generators;Field programmable gate arrays;NIST;Chaos;Software;IP networks;Batteries;PRNG;random;chaos;Henon;FPGA;Zynq;NIST
@inproceedings{8583863,
title = {FPGA Implementation of a Chaos Based PRNG Targetting Secret Communication},
author = {Radu Hobincu and Octaviana Datcu},
doi = {10.1109/ISETC.2018.8583863},
issn = {2475-7861},
year = {2018},
date = {2018-11-01},
booktitle = {2018 International Symposium on Electronics and Telecommunications (ISETC)},
pages = {1-4},
abstract = {This paper describes the digital implementation of a chaos based cyptographic pseudo-random number generator using a Zynq SoC, offloading the computation to the FPGA. The implementation is based on the generalized Henon map, and it is done using fixed point 3.61 arithmetic. We will show that there is a performance improvement compared to the execution on the ARM Cortex A9 processor and that the generated random bytes are consistent with the software implementation. The generator is tested against the NIST, Dieharder and TestU01 suites.},
keywords = {Generators;Field programmable gate arrays;NIST;Chaos;Software;IP networks;Batteries;PRNG;random;chaos;Henon;FPGA;Zynq;NIST},
pubstate = {published},
tppubtype = {inproceedings}
}
This paper describes the digital implementation of a chaos based cyptographic pseudo-random number generator using a Zynq SoC, offloading the computation to the FPGA. The implementation is based on the generalized Henon map, and it is done using fixed point 3.61 arithmetic. We will show that there is a performance improvement compared to the execution on the ARM Cortex A9 processor and that the generated random bytes are consistent with the software implementation. The generator is tested against the NIST, Dieharder and TestU01 suites.