1.
Popescu, George-Vlăduţ; Bîră, Călin
Python-Based Programming Framework for a Heterogeneous MapReduce Architecture Proceedings Article
In: 2022 14th International Conference on Communications (COMM), pp. 1-6, 2022.
Abstract | Links | BibTeX | Tags: Software packages;Linear algebra;Computer architecture;Programming;Writing;Data transfer;Libraries;Heterogeneous computing;MapReduce Accelerator;ARM-FPGA;software library;framework
@inproceedings{9817183,
title = {Python-Based Programming Framework for a Heterogeneous MapReduce Architecture},
author = {George-Vlăduţ Popescu and Călin Bîră},
doi = {10.1109/COMM54429.2022.9817183},
year = {2022},
date = {2022-06-01},
booktitle = {2022 14th International Conference on Communications (COMM)},
pages = {1-6},
abstract = {This paper presents a low-maintenance, short development-cycle programming framework (MRAFW) which allows writing and running software for a custom heterogeneous pseudo-reconfigurable computing system integrating a MapReduce Accelerator. The target system implementation is based on AMD/Xilinx's Zynq SoC hardware platform. The programming framework uses the PYNQ software package to enable access to the system resources and to manage CPU-FPGA program and data transfers. Furthermore, we provide a library of optimized low-level functions that offer support for executing some basic linear algebra operations.},
keywords = {Software packages;Linear algebra;Computer architecture;Programming;Writing;Data transfer;Libraries;Heterogeneous computing;MapReduce Accelerator;ARM-FPGA;software library;framework},
pubstate = {published},
tppubtype = {inproceedings}
}
This paper presents a low-maintenance, short development-cycle programming framework (MRAFW) which allows writing and running software for a custom heterogeneous pseudo-reconfigurable computing system integrating a MapReduce Accelerator. The target system implementation is based on AMD/Xilinx's Zynq SoC hardware platform. The programming framework uses the PYNQ software package to enable access to the system resources and to manage CPU-FPGA program and data transfers. Furthermore, we provide a library of optimized low-level functions that offer support for executing some basic linear algebra operations.