Publications

@inproceedings{6095808,

title = {Backus language for functional nano-devices},

author = {Mihaela Maliţa and Gheorghe M. Ştefan},

doi = {10.1109/SMICND.2011.6095808},

issn = {2377-0678},

year  = {2011},

date = {2011-10-01},

booktitle = {CAS 2011 Proceedings (2011 International Semiconductor Conference)},

volume = {2},

pages = {331-334},

abstract = {The emergent nano-technologies must be used to design functional nano-devices with complexity in the range of their size. The way to achieve this goal is to define parallel programmable engines. The concept of FP System, introduced by John Backus in 1978, is used to define a high level architectural environment: Backus-Connex Parallel Functional Programming System. The functional forms of FP Systems correspond perfect with the four types of parallelism derived for ConnexArray™ from the Kleene's computational model. The paper defines the BC programming environment, describes its implementation in Scheme and presents its use for developing real applications for functional nano-devices.},

keywords = {Parallel processing;Vectors;Complexity theory;Functional programming;Arrays;nano-electronics;functional electronics;programmable circuits;parallelism;functional programming},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{WOS:000320322000075,

title = {BACKUS LANGUAGE FOR FUNCTIONAL NANO-DEVICES},

author = {Mihaela Malita and Gheorghe M. Stefan},

issn = {1545-827X},

year  = {2011},

date = {2011-01-01},

booktitle = {2011 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS 2011), 34TH EDITION, 

 VOLS 1 AND 2},

pages = {331-334},

publisher = {IEEE},

address = {345 E 47TH ST, NEW YORK, NY 10017 USA},

organization = {IEEE; IEEE Electron Devices Soc (EDS); Minist Educ, Res, Youth & Sport; 

 IEEE Romanian Sect; IEEE Electron Devices Chapter; Romanian Acad; 

 Electrochem Soc Inc; Raith-Innovat Solut Nanofabricat & Semicond 

 Inavigat (Raith); Oxford Instruments GmbH Plasma Technol; S C Style Serv 

 S R L},

series = {International Semiconductor Conference},

abstract = {The emergent nano-technologies must be used to design functional 

 nano-devices with complexity in the range of their size. The way to 

 achieve this goal is to define parallel programmable engines. The 

 concept of FP System, introduced by John Backus in 1978, is used to 

 define a high level architectural environment: Backus-Connex Parallel 

 Functional Programming System. The functional forms of FP Systems 

 correspond perfect with the four types of parallelism derived for 

 ConnexArray (TM) from the Kleene's computational model. The paper 

 defines the BC programming environment, describes its implementation in 

 Scheme and presents its use for developing real applications for 

 functional nano-devices.},

note = {34th International Semiconductor Conference (CAS), Natl Inst Res & Dev 

 Microtechnologies (IMT), Sinaia, ROMANIA, OCT 17-19, 2011},

keywords = {nano-electronics; functional electronics; programmable circuits;   parallelism; functional programming},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{5679319,

title = {Performance gain from data and control dependency elimination in embedded processors},

author = {Valeriu Codreanu and Radu Hobincu},

doi = {10.1109/ISETC.2010.5679319},

year  = {2010},

date = {2010-11-01},

booktitle = {2010 9th International Symposium on Electronics and Telecommunications},

pages = {47-50},

abstract = {This paper presents a way of increasing overall performance in embedded processors by introducing a multithreading interleaved execution model that can be applied to any Instruction Set Architecture. Usual acceleration techniques as superpipeline or branch prediction are not suited for embedded machines due to their inherent inefficiency. We will show that by removing dependencies within a processor and thus eliminating the need for extra hardware required for keeping the overall coherence, there will be a noticeable increase in performance (up to 450%) and also a decrease in size and power consumption. Also, this approach will maintain the backwards compatibility with the software legacy in order to keep the software changes to a minimum.},

keywords = {Pipelines;Computer architecture;Instruction sets;Hazards;Multithreading;Registers;embedded;processor;interleaved;multithreading},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{5650942,

title = {Technology driven architecture for integral parallel embedded computing},

author = {Petronela Bumbăcea and Valeriu Codreanu and Radu Hobincu and Lucian Petrică and Gheorghe M. Ştefan},

doi = {10.1109/SMICND.2010.5650942},

issn = {2377-0678},

year  = {2010},

date = {2010-10-01},

booktitle = {CAS 2010 Proceedings (International Semiconductor Conference)},

volume = {01},

pages = {35-42},

abstract = {The computational structures are not able to scale following the increased number of components offered by the technological development driven by the Moore's law. In order to use efficiently the emerging nanotechnologies new architectural approaches are requested. Thus, new technology driven architectures must be developed. The proposed architecture is designed in this technologically evolving context, to support the increasing computational diversity, complexity and intensity requested in the emergent domain of parallel embedded computing. The resulting physical embodiment has at least two orders of magnitude higher effective GIPS/Watt and GIPS/mm2 than the currently produced structures. This new architectural approach is based on ConnexArray™ technology, already developed and tested on real chips, and on the Bubble-free Embedded Architecture for Multithreading execution model. The paper proposes a computational platform able to manage tens of threads and a number of execution/processing units which starts from tens and goes up to thousands.},

keywords = {Instruction sets;Complexity theory;Computational modeling;Computational efficiency;Embedded computing;Organizations;Computer architecture},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{5595168,

title = {Matrix computation on Connex Parallel Architecture},

author = {Ana-Maria Calfa and Gheorghe Stefan},

year  = {2010},

date = {2010-09-01},

booktitle = {ICSES 2010 International Conference on Signals and Electronic Circuits},

pages = {375-378},

abstract = {The parallel Connex Architecture has specific features imposed in order to improve GIPS/Watt and GIPS/mm2. It is designed for embedded computation in systems on chip design. Its validation supposes exploring by turn different application domains to see how the specific architectural and design assumptions affected the actual performance. In this paper the domain of matrix computation is preliminary investigated.},

keywords = {Arrays;Acceleration;Parallel processing;Parallel architectures;HDTV;System-on-a-chip},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{WOS:000371396100005,

title = {TECHNOLOGY DRIVEN ARCHITECTURE FOR INTEGRAL PARALLEL EMBEDDED COMPUTING},

author = {Petronela Bumbacea and Valeriu Codreanu and Radu Hobincu and Lucian Petrica and Gheorghe M. Stefan},

issn = {1545-827X},

year  = {2010},

date = {2010-01-01},

booktitle = {2010 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), VOLS 1 AND 2},

pages = {35-42},

publisher = {IEEE},

address = {345 E 47TH ST, NEW YORK, NY 10017 USA},

organization = {Inst Elect & Elect Engineers; IEEE Elect Devices Soc; Minist Educ Youth 

 & Sports; IEEE Romania Sect; Elect Device Chapter; Natl Inst Res & Dev 

 Microtechnologies; Centrotherm Thermal Solut GmbH Co KG},

series = {International Semiconductor Conference},

abstract = {The computational structures are not able to scale following the 

 increased number of components offered by the technological development 

 driven by the Moore's law. In order to use efficiently the emerging 

 nanotechnologies new architectural approaches are requested. Thus, new 

 technology driven architectures must be developed. The proposed 

 architecture is designed in this technologically evolving context, to 

 support the increasing computational diversity, complexity and intensity 

 requested in the emergent domain of parallel embedded computing. The 

 resulting physical embodiment has at least two orders of magnitude 

 higher effective GIPS/Watt and GIPS/mm(2) than the currently produced 

 structures. This new architectural approach is based on ConnexArray (TM) 

 technology, already developed and tested on real chips, and on the 

 Bubble-free Embedded Architecture for Multithreading execution model. 

 The paper proposes a computational platform able to manage tens of 

 threads and a number of execution/processing units which starts from 

 tens and goes up to thousands.},

note = {33rd International Semiconductor Conference (CAS), Sinaia, ROMANIA, OCT 

 11-13, 2010},

keywords = {},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{5200028,

title = {Integral Parallel Architecture & Berkeley's Motifs},

author = {Mihaela Malita and Gheorghe Stefan},

doi = {10.1109/ASAP.2009.40},

issn = {1063-6862},

year  = {2009},

date = {2009-07-01},

booktitle = {2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors},

pages = {191-194},

abstract = {The integral parallel architecture (IPA) developed and actually implemented by BrightScale is a low-power (133 GOPS1/Watt) & low-area (8 GOPS/mm2) one-chip solution to solve intense computational problems using data-parallel, time-parallel and speculative-parallel mechanisms. BrightScale technology is presented from the point of view of each of the 13 motifs proposed in The Berkeley's View. IPA emerges from Kleene's computational model of the partial recursive functions as the simplest parallel architecture, a good starting point for a true science of parallel computation. We briefly investigate how such an elementary parallel architecture performs, for the main computational motifs, in solving the problems of programmability, portability, flexibility, data movement between computational cells, and between cells and the main memory.},

keywords = {Parallel architectures;parallel computing;integral parallel architecture;SoC},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{4519770,

title = {Stacks or File-Registers in Cellular Computing?},

author = {Marius Stoian and Gheorghe Stefan},

doi = {10.1109/SMICND.2007.4519770},

issn = {2377-0678},

year  = {2007},

date = {2007-10-01},

booktitle = {2007 International Semiconductor Conference},

volume = {2},

pages = {501-504},

abstract = {Stack oriented architectures are compared with register file oriented architectures in order to decide what is the best for building cellular programmable machines. Area & power vs. computing performance are investigated considering two kind of "users" (i) a compiler, which is another machine, and (ii) a human mind, writing hand coded programs.},

keywords = {Clocks;Computer architecture;Registers;Hardware design languages;Humans;Arithmetic;Logic;Wire;Consumer electronics;Electronic mail},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{WOS:000243090700091,

title = {The three valued logic implementation on a hybrid SOI structure},

author = {Cristian Ravariu and Hascsi Zoltan and Florina Ravariu and Lidia Dobrescu},

isbn = {1-4244-0109-7},

year  = {2007},

date = {2007-01-01},

booktitle = {2006 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOLS 1 AND 2},

pages = {425+},

publisher = {IEEE},

address = {345 E 47TH ST, NEW YORK, NY 10017 USA},

organization = {Natl Inst Res & Dev Microtechnologies; Romanian Acad Electrochem Soc; 

 IEEE Electron Devices Soc; Minist Educ & Res; IEEE Romanian Sect; IEEE, 

 Elect Devices Chapter},

abstract = {Diamond versus silicon gives a higher threshold voltage, due to its 

 wider band gap. For a logic application this means pushing up the 1(st) 

 logic level toward a 2(-nd) logic level on DOI device. A hybrid 

 structure both with silicon and diamond on insulator opens the door 

 toward the three-valued logic with very stable states for 0-level, I 

 level and 2-level. In digital circuits is very important to have 

 distinct and stable logic levels. The individuality of logic levels is 

 ensured by two different materials: Silicon and Diamond.},

note = {29th International Semiconductor Conference (CAS 2006), Sinaia, ROMANIA, 

 SEP 27-29, 2006},

keywords = {SOI / DOI structures; basic 3-valued functions; MISFET},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{4063264,

title = {The Three Valued Logic Implementation on a Hybrid SOI Structure},

author = {Cristian Ravariu and Hascsi Zoltan and Florina Ravariu and Lidia Dobrescu},

doi = {10.1109/SMICND.2006.284036},

issn = {2377-0678},

year  = {2006},

date = {2006-09-01},

booktitle = {2006 International Semiconductor Conference},

volume = {2},

pages = {425-428},

abstract = {Diamond versus silicon gives a higher threshold voltage, due to its wider band gap. For a logic application this means pushing up the 1 -st logic level toward a 2-nd logic level on DOI device. A hybrid structure both with silicon and diamond on insulator opens the door toward the three valued logic with very stable states for 0-level, 1-level and 2-level. In digital circuits is very important to have distinct and stable logic levels. The individuality of logic levels is ensured by two different materials: silicon and diamond},

keywords = {Logic devices;MOSFETs;Multivalued logic;Combinational circuits;Threshold voltage;Silicon on insulator technology;Insulation;Digital circuits;Logic circuits;Humans;SOI / DOI structures;basic 3-valued functions;MISFET},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{7477854,

title = {The CA1024: A fully programmable system-on-chip for costeffective HDTV media processing},

author = {Lazar Bivolarski and Bogdan Mitu and Anand Sheel and Gheorghe Stefan and Tom Thomson and Dan Tomescu},

doi = {10.1109/HOTCHIPS.2006.7477854},

year  = {2006},

date = {2006-08-01},

booktitle = {2006 IEEE Hot Chips 18 Symposium (HCS)},

pages = {1-26},

abstract = {This article consists of a collection of slides from the author's conference presentation onConnex's CA1024, a fully programmable system-on-chip HDTV media processing system. Some of the specific topics discussed include: the special features and specifications of CA1024; deployment and applications for it use; media processing capabilities; and performance evaluation for system processing.},

keywords = {HDTV;Process control;Random access memory;System-on-chip;Media},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{4124069,

title = {Local Alignments of DNA Sequences with the Connex Array},

author = {Dominique Thiebaut and Gheorghe Stefan and Mihaela Malita},

doi = {10.1109/ICCGI.2006.47},

year  = {2006},

date = {2006-08-01},

booktitle = {2006 International Multi-Conference on Computing in the Global Information Technology - (ICCGI'06)},

pages = {50-50},

abstract = {This paper presents a heuristic for finding close to optimal solutions to the local alignment problem of two DNA sequences, and more precisely to the gene prediction problem on the Connex Array circuit, a new hierarchical parallel in-memory device. Though not optimal, the solutions generated by our algorithm compare well with those generated by other algorithms in the public domain. When aligning a probe of N symbols to a target of M symbols, the algorithm has a theoretical time complexity of O(N log(N)), with a small constant of proportionality, and requires no preprocessing of the data. However, experimental results exhibit quasi-linear time complexity.},

keywords = {DNA;Sequences;Circuits;Random access memory;Computer science;Educational institutions;Space technology;Probes;Read-write memory;Clocks},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{4124045,

title = {Complex vs. Intensive in Parallel Computation},

author = {Michaela Malita and Gheorghe Stefan and Marius Stoian},

doi = {10.1109/ICCGI.2006.16},

year  = {2006},

date = {2006-08-01},

booktitle = {2006 International Multi-Conference on Computing in the Global Information Technology - (ICCGI'06)},

pages = {26-26},

abstract = {The distinction between complex computation and intensive computation becomes more meaningful now, when all high performance computing machines are de facto parallel machines. The distinction is stated by introducing the concept of integral parallel computation as the most natural and efficient way to increase the performance using all kinds of parallel computations. A new functional taxonomy of parallel machines is used to support the integral approach. Finally, the new concepts and distinctions are exemplified describing the Connex Architecture and its first embodiment: the video-chip CA1024 launched by Connex Technology, Inc.},

keywords = {Concurrent computing;Taxonomy;Parallel processing;Pervasive computing;High performance computing;Parallel machines;Circuits;Parallel architectures;Embedded computing;Educational institutions},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{1558827,

title = {Virtual environment for robots interfaces design and testing},

author = {E. Franti and D. Tufis and S. Goschin and M. Dascalu and P. L. Milea and G. Stefan and T. Balan and C. Slav and R. Demco},

doi = {10.1109/SMICND.2005.1558827},

issn = {2377-0678},

year  = {2005},

date = {2005-10-01},

booktitle = {CAS 2005 Proceedings. 2005 International Semiconductor Conference, 2005.},

volume = {2},

pages = {463-466 vol. 2},

abstract = {This paper refers to the implementation of a virtual environment for the robot interfaces testing. This software environment is very useful because, comparing to the experiments with real robots, it allow the testing and evaluation of different types of interfaces and different working environments with diverse configurations. A very important facility of this interactive software environment is the fact that the designers of the robots sensors and interfaces are able to work in parallel to design test, optimize and realize different control devices for the robot.},

keywords = {Virtual environment;Robot sensing systems;Artificial intelligence;Intelligent robots;Mobile robots;Electronic equipment testing;Software testing;Parallel robots;Robot control;Education},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{1558807,

title = {A multithreading architecture for low power processors},

author = {M. Stoian and G. Stefan},

doi = {10.1109/SMICND.2005.1558807},

issn = {2377-0678},

year  = {2005},

date = {2005-10-01},

booktitle = {CAS 2005 Proceedings. 2005 International Semiconductor Conference, 2005.},

volume = {2},

pages = {387-390 vol. 2},

abstract = {In this paper a multithreading architecture is proposed as a solution for the computing that has to be done using very limited power resources. The proposed structure supports four threads, all threads being available for the user computation. Using a multithreading architecture the power consumption is decreased considerably by removing the resources for speculation and ILP extraction. Reducing the die area as much as possible the cell's internal power is reduced. Increasing the degree of utilization of the available hardware resources the net's switching power is considerably reduced. We will show how a multithreading architecture can achieve these two goals without any decreasing in computing performance},

keywords = {Multithreading;Yarn;Hardware;Computer architecture;Switches;Java;Energy consumption;Circuits;Clocks;Frequency},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{1558751,

title = {Artificial muscle for locomotory prosthesis},

author = {T. Balan and E. Franti and T. Alexa and D. Tufis and G. Stefan and N. Claudia and P. L. Milea and C. Slav and R. Demco},

doi = {10.1109/SMICND.2005.1558751},

issn = {2377-0678},

year  = {2005},

date = {2005-10-01},

booktitle = {CAS 2005 Proceedings. 2005 International Semiconductor Conference, 2005.},

volume = {1},

pages = {215-218 vol. 1},

abstract = {One of the hopes, of the scientific frontier domains tangent with the artificial intelligence is and will probably remain for a long time, the realization of the artificial prosthesis and organs which could compensate for the people the incurable consequences of some accidents or severe diseases. From all the types of prosthesis existent on the market in the present, only 1% have implemented electronic devices for the controlling and command of the movements and these only for the big dimensions segments (elements of the elbow articulation, knee etc). The system which is presented in this paper allow a personalized design of the prothesis according to the characteristics and the specific needs of the patient. This system allowed the authors to design, test and implement two intelligent prothesis for legs which are also presented in this paper. The intelligent structure of these prothesis include pressure sensors, position sensors and microcontrollers. The mechanical structure of these prothesis was realized from articulated segments of composite and metallic materials and for the artificial muscular system was used pneumatic muscles.},

keywords = {Muscles;Prosthetics;Intelligent sensors;Artificial intelligence;Mechanical sensors;Sensor phenomena and characterization;Accidents;Diseases;Consumer electronics;Elbow},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{890221,

title = {Low-power oriented microcontroller architecture},

author = {B. Mitu and G. Stefan},

doi = {10.1109/SMICND.2000.890221},

year  = {2000},

date = {2000-10-01},

booktitle = {2000 International Semiconductor Conference. 23rd Edition. CAS 2000 Proceedings (Cat. No.00TH8486)},

volume = {1},

pages = {215-218 vol.1},

abstract = {A new criterion becomes more and more important in digital design: the power. Related criteria such as size, speed, complexity, testability, and the power consumption criterion are imposed by the requirements of "mobile electronics". On the other side, microcontroller technology is involved and will be involved in almost all current solutions offered by electronics. The flexibility of use of microcontrollers increases if all internal functions are performed by programs. The "virtual peripheral" is the best solution that maintains the microcontroller complexity at a low level. This approach seems to be a contradictory one. Building all the functions by programs wastes power in the standard approach. Our goal is to offer a solution that satisfies both the flexibility of programmed solutions and the low-power design criterion. The paper presents power-aware design principles for microcontrollers with virtual peripherals, used for programmed logic applications.},

keywords = {Microcontrollers;Computer peripherals;Computer architecture;Electronic equipment testing;Application software;Circuits;Yarn;Buildings;Logic devices;Performance evaluation},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{810524,

title = {A processor network without interconnection path},

author = {D. Stefan and G. Stefan},

doi = {10.1109/SMICND.1999.810524},

year  = {1999},

date = {1999-10-01},

booktitle = {CAS '99 Proceedings. 1999 International Semiconductor Conference (Cat. No.99TH8389)},

volume = {1},

pages = {305-308 vol.1},

abstract = {In the current silicon technologies the wire connections become more and more important. They will waste time, energy and maybe area more than the gates. Beyond the technological solutions for this problem, architectural solutions are welcome. This paper discusses a solution which completely avoids the interconnections in a 4-processor network. More, the four processors share many structural resources, thus minimizing the size of the entire structure. The pipeline penalties are completely avoided in the proposed structure. The machine we describe is an environment for interleaved multi-threaded executions.},

keywords = {Clocks;Pipelines;Frequency;Algorithm design and analysis;Circuit testing;Yarn;Reduced instruction set computing;Counting circuits;Registers;Logic testing},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{733816,

title = {Looking for the lost noise},

author = {G. Stefan},

doi = {10.1109/SMICND.1998.733816},

year  = {1998},

date = {1998-10-01},

booktitle = {1998 International Semiconductor Conference. CAS'98 Proceedings (Cat. No.98TH8351)},

volume = {2},

pages = {579-582 vol.2},

abstract = {The noise can be very well approximated using a simple circuit and a sophisticated rule. We propose a simple, recursively defined, big circuit that, starting from own autonomy, generates pseudo-noise. To the well known method of using cellular automaton in order to generate pseudo-random sequences some new features are added in order to improve the "random" behaviour. The randomness results in a chaotic process, very sensible to the initial state of a simple machine working after a strange rule. The proposed structure claims a huge amount of work in order to find an appropriate initial state according to tire noise "characteristics". The initial state must be selected from a space having 2/sup 256/ points. Only the genetic algorithms offers us the illusion of finding the best point in this huge space.},

keywords = {Circuit noise;Automata;Chaos;Noise generators;Fractals;Logic functions;Genetic programming;Proposals;Binary sequences;Input variables},

pubstate = {published},

tppubtype = {inproceedings}

}