Publications

@inproceedings{WOS:000641147900094,

title = {Parallel Machine Simulator Using Racket/Scheme Functional Programming 

 Language},

author = {Calin Bira and Liviu Gugu},

editor = {M Vladescu and R Tamas and I Cristea},

doi = {10.1117/12.2572096},

issn = {0277-786X},

year  = {2020},

date = {2020-01-01},

booktitle = {ADVANCED TOPICS IN OPTOELECTRONICS, MICROELECTRONICS AND 

 NANOTECHNOLOGIES X},

volume = {11718},

publisher = {SPIE-INT SOC OPTICAL ENGINEERING},

address = {1000 20TH ST, PO BOX 10, BELLINGHAM, WA 98227-0010 USA},

organization = {Minist Res & Innovat; Univ Politehnica Bucharest, Optoelectron Res Ctr; 

 Maritime Univ Constanta},

series = {Proceedings of SPIE},

abstract = {In this paper we investigate writing and using of a functional 

 parallel-machine simulator, in a functional programming language as 

 opposed to an imperative programming language, in terms of code-size, 

 versatility and performance. As a use-case we chose a SIMD-type machine, 

 and the Racket/Scheme programming language,. The main advantages over 

 the use of imperative programming languages for creating architectural 

 simulators are (i)divided by the loose coupling to the architecture and 

 (ii) the lack of an explicit compiler. By attempting two common software 

 implementations and some changes to the base architecture we argue that 

 the simulator is better in terms of algorithm-code size and system 

 versatility (number of required changes for extending functionality) but 

 not in execution speed (as it is running on a von Neumann machine, where 

 C++ code is compiled into native machine code, not interpreted)},

note = {Conference on Advanced Topics in Optoelectronics, Microelectronics and 

 Nanotechnologies X, Constanta, ROMANIA, AUG 20-23, 2020},

keywords = {Lisp; Scheme; functional programming language; parallel machine   functional simulator},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{WOS:000641147900105,

title = {TL-TensorFlow CNN model and dataset for electronic equipment},

author = {Calin Bira and Valentin-Gabriel Voiculescu},

editor = {M Vladescu and R Tamas and I Cristea},

doi = {10.1117/12.2572157},

issn = {0277-786X},

year  = {2020},

date = {2020-01-01},

booktitle = {ADVANCED TOPICS IN OPTOELECTRONICS, MICROELECTRONICS AND 

 NANOTECHNOLOGIES X},

volume = {11718},

publisher = {SPIE-INT SOC OPTICAL ENGINEERING},

address = {1000 20TH ST, PO BOX 10, BELLINGHAM, WA 98227-0010 USA},

organization = {Minist Res & Innovat; Univ Politehnica Bucharest, Optoelectron Res Ctr; 

 Maritime Univ Constanta},

series = {Proceedings of SPIE},

abstract = {This paper proposes a solution for classification of electronics 

 laboratory equipment with emphasis on the electronic laboratory tools / 

 equipment. It uses transfer-learning applied to the pretrained 

 Inception-V3 network model. A study regarding the impact of small 

 retrain dataset is conducted to see its impact in transfer-learning over 

 Inception-V3 network model.},

note = {Conference on Advanced Topics in Optoelectronics, Microelectronics and 

 Nanotechnologies X, Constanta, ROMANIA, AUG 20-23, 2020},

keywords = {CNN; transfer learning; Inception-v3; classify electronic equipement},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{WOS:000641147900095,

title = {Functional Simulator for Sensor-based Embedded Systems},

author = {Calin Bira},

editor = {M Vladescu and R Tamas and I Cristea},

doi = {10.1117/12.2572098},

issn = {0277-786X},

year  = {2020},

date = {2020-01-01},

booktitle = {ADVANCED TOPICS IN OPTOELECTRONICS, MICROELECTRONICS AND 

 NANOTECHNOLOGIES X},

volume = {11718},

publisher = {SPIE-INT SOC OPTICAL ENGINEERING},

address = {1000 20TH ST, PO BOX 10, BELLINGHAM, WA 98227-0010 USA},

organization = {Minist Res & Innovat; Univ Politehnica Bucharest, Optoelectron Res Ctr; 

 Maritime Univ Constanta},

series = {Proceedings of SPIE},

note = {Conference on Advanced Topics in Optoelectronics, Microelectronics and 

 Nanotechnologies X, Constanta, ROMANIA, AUG 20-23, 2020},

keywords = {C plus; system-level functional simulator; embedded; sensor model},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{WOS:000641147900108,

title = {Performance-oriented PIC10F N-core simulator},

author = {Bogdan Petric and Calin Bira},

editor = {M Vladescu and R Tamas and I Cristea},

doi = {10.1117/12.2572231},

issn = {0277-786X},

year  = {2020},

date = {2020-01-01},

booktitle = {ADVANCED TOPICS IN OPTOELECTRONICS, MICROELECTRONICS AND 

 NANOTECHNOLOGIES X},

volume = {11718},

publisher = {SPIE-INT SOC OPTICAL ENGINEERING},

address = {1000 20TH ST, PO BOX 10, BELLINGHAM, WA 98227-0010 USA},

organization = {Minist Res & Innovat; Univ Politehnica Bucharest, Optoelectron Res Ctr; 

 Maritime Univ Constanta},

series = {Proceedings of SPIE},

abstract = {Testing of multiple programs running on the same core architecture is of 

 use when a new microcontroller architecture is developed. However, this 

 is performed sequentially even if the microcontroller to be developed is 

 of very small compute power, making the testbench setup time dominate 

 test runtime. This paper proposes a solution for testing multiple 

 programs (hex-files) based on the PIC10F family [1] of MCUs from 

 Microchip. A performance comparison will be made against the Microchip's 

 MPLAB Simulator taking multiple precautions to enable a fair comparison.},

note = {Conference on Advanced Topics in Optoelectronics, Microelectronics and 

 Nanotechnologies X, Constanta, ROMANIA, AUG 20-23, 2020},

keywords = {performance-oriented simulator; PIC10F},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{WOS:000646194100010,

title = {eHealth Perspective Co-designed and Implemented with Romanian Elders for 

 Independent Living},

author = {Cristian Vizitiu and Calin Bira and Adrian Dinculescu and Mihai Mandu and Alexandru Nistorescu and Mihaela Marin},

issn = {2575-5137},

year  = {2020},

date = {2020-01-01},

booktitle = {2020 INTERNATIONAL CONFERENCE ON E-HEALTH AND BIOENGINEERING (EHB)},

publisher = {IEEE},

address = {345 E 47TH ST, NEW YORK, NY 10017 USA},

organization = {IEEE; SRBM; IEEE EMB Romanian Sect Chapter; IEEE Romanian Sect; Grigore 

 T Popa Univ Med & Pharm, Fac Med Bioengineering; Romanian Soc Med 

 Bioengineering Iasi; Romanian Acad Iasi Branch, Inst Comp Sci; Constanta 

 Maritime Univ; IEEE EMC Romania Chapter; IEEE Signal Proc Romania 

 Chapter; IEEE SMC Romania Chapter},

series = {E-Health and Bioengineering Conference},

abstract = {Given the context of 20% increased number of individuals over 60 years 

 till 2030 and further, there is emerging a real need to support elderly 

 people in independent living while eHealth technologies proved to be 

 promising solutions in this role. The paper presents an eHealth solution 

 via co-design and Proof of Concept (PoC) perspective on Romanian elders, 

 demarches led within the international Active and Assisted Living (AAL) 

 Programme endorsing ``smart solutions for ageing well'' vision. The 

 eHealth solution, based on open source hardware for interoperability and 

 scalability, supports elders to collect biometric information at home 

 and further provides this info to the corresponding 

 caregivers/volunteers when needed in order to take actions accordingly 

 in proper time. The eHealth system, planned according to Systems 

 Engineering methodology, took in consideration Romanian end-user 

 requirements whose verifications were performed via a PoC 

 implementation. Subsequently the concept will become more comprehensive 

 after several co-design sessions planned to be performed also in Hungary 

 and Italy, partner countries in AAL project consortium.},

note = {8th International Conference on E-Health and Bioengineering (EHB), 

 ELECTR NETWORK, OCT 29-30, 2020},

keywords = {eHealth; elders; biometric information; Systems Engineering (SE); Active   and Assisted Living Programme (AAL)},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{WOS:000637264600028,

title = {Multi-Function Scan Circuit},

author = {Mihai Antonescu and Gheorghe M. Stefan},

editor = {I Stavarache and G Stefan and T Stoica and A Takacs and A Tulbure and ML Veca and T Visan and RC Voicu and G Brezeanu and ML Ciurea and D Cristea and MA Dinescu and D Dobrescu and M Dragoman and A Muller and R Muller and D Neculoiu},

doi = {10.1109/cas50358.2020.9268048},

issn = {1545-827X},

year  = {2020},

date = {2020-01-01},

booktitle = {CAS 2020 PROCEEDINGS: 2020 INTERNATIONAL SEMICONDUCTOR CONFERENCE},

pages = {123-126},

publisher = {IEEE},

address = {345 E 47TH ST, NEW YORK, NY 10017 USA},

organization = {Natl Inst Res & Dev Microtehnologies IMT Bucharest; IEEE Electron 

 Devices Soc; Minist Educ & Res; Guvernul Romaniei},

series = {International Semiconductor Conference},

abstract = {The practice of parallel computing emphasizes frequently used patterns. 

 Some of them can be accelerated using appropriate networks of simple 

 circuits. We propose a solution, based on the frame offered by the Benes 

 permutation network. It is adapted to efficiently accelerate some of the 

 most used parallel computation patterns: prefix, split, reduction. The 

 cells of the Benes network associated to a Map pattern of n units are 

 designed to support the additional functions. Two versions are 

 considered: a log-depth pipelined version and a sequential, iterative 

 version.},

note = {43rd International Semiconductor Conference (CAS), ELECTR NETWORK, OCT 

 07-09, 2020},

keywords = {scan; reduction; prefix; permute; split},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{WOS:000662554705026,

title = {Pseudo-Reconfigurable Heterogeneous Solution for Accelerating Spectral 

 Clustering},

author = {Mihaela Malita and George Vladut Popescu and Gheorghe M. Stefan},

editor = {XT Wu and C Jermaine and L Xiong and XH Hu and O Kotevska and SY Lu and WJ Xu and S Aluru and CX Zhai and E Al-Masri and ZY Chen and J Saltz},

doi = {10.1109/BigData50022.2020.9378150},

issn = {2639-1589},

year  = {2020},

date = {2020-01-01},

booktitle = {2020 IEEE INTERNATIONAL CONFERENCE ON BIG DATA (BIG DATA)},

pages = {5138-5145},

publisher = {IEEE},

address = {345 E 47TH ST, NEW YORK, NY 10017 USA},

organization = {IEEE; IEEE Comp Soc; IBM; Ankura},

series = {IEEE International Conference on Big Data},

abstract = {Spectral clustering is a Machine Learning technique intensively used in 

 Big Data applications. It makes extensive use of linear algebra. This 

 article introduces the concept of MapReduce Accelerator (MRA) as the 

 reconfigurable part of a heterogeneous computing system. Although the 

 accelerator we propose is a general purpose one, it has some specific 

 features related to the targeted application. This is possible due to 

 the pseudo-reconfigurable environment which deploys in FPGA a 

 parameterizable programmable accelerator. The main specific 

 characteristics of the accelerator are proposed as a result of the 

 analysis performed on the spectral clustering algorithms. The 

 architecture is described and the spectral clustering algorithms are 

 evaluated. The proposed solution is compared, in terms of computing 

 performance and energy consumption, with other solutions published in 

 the literature. The increase in computing performance is accompanied by 

 a 3-5 times reduction in energy consumed. The accelerator is a linear 

 array of cells controlled by a sequencer loop closed through a reduction 

 network. Each cell is a simple, accumulator-based execution unit with a 

 big two-port register file. The reduction network is a log-depth 

 pipelined circuit performing few reduction functions such as add, min, 

 max. The experimental system is a PYNQ-Z2 board equipped with Zinq 7020 

 SoC; it is used to implement and evaluate the acceleration provided by 

 an 128-cell MRA.},

note = {8th IEEE International Conference on Big Data (Big Data), ELECTR 

 NETWORK, DEC 10-13, 2020},

keywords = {Spectral clustering; parallel algorithm; parallel computing;   accelerator; heterogeneous computing; pseudo-reconfigurable computing},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{9071100,

title = {Heterogeneous Computing for Markov Models in Big Data},

author = {Mihaela Malita and George Vladut Popescu and Gheorghe M. Stefan},

doi = {10.1109/CSCI49370.2019.00279},

year  = {2019},

date = {2019-12-01},

booktitle = {2019 International Conference on Computational Science and Computational Intelligence (CSCI)},

pages = {1500-1505},

abstract = {Many Big Data problems, Markov Model related included, are solved using heterogenous systems: host + parallel programmable accelerator. The current solutions for the accelerator part - for example, GPU used as GPGPU - provide limited accelerations due to some architectural constraints. The paper introduces the use of a programmable parallel accelerator able to perform efficient vector and matrix operations avoiding the limitations of the current systems designed using "of-theshelf" solutions. Our main result is an architecture whose actual performance is a much higher percentage from its peak performance than those of the consecrated accelerators. The performance improvements we offer come from the following two features: the addition of a reduction network at the output of a linear array of cells and an appropriate use of a serial register distributed along the same linear array of cells. Thus, for a n-state Markov Model, instead of a solution with the size in O(n2) and an acceleration in O(n2=logn), we offer an accelerator with the size in O(n) and the acceleration in O(n).},

keywords = {Hidden Markov models;Graphics processing units;Acceleration;Computational modeling;Markov processes;Viterbi algorithm;Data models;Big data;Markov models;parallel architecture;accelerators;hetrogenous computing},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{8923805,

title = {Singular value decomposition to determine the dynamics of a chaotic regime oscillator},

author = {Octaviana Datcu and Radu Hobincu and Corina Macovei},

doi = {10.1109/SMICND.2019.8923805},

issn = {2377-0678},

year  = {2019},

date = {2019-10-01},

booktitle = {2019 International Semiconductor Conference (CAS)},

pages = {119-122},

abstract = {Targeting the hybrid analog-digital private communication field, this paper aims to estimate the parameters of an analog circuit model. An oscilloscope stores the samples of a voltage in a.csv file. The data series is processed using a digital signal technique the singular value decomposition. Singular values and corresponding right-eigenvectors are used to estimated the values of the parameters of the model characterizing the circuit that produced the measured output. The decomposition is performed using small windows of samples of the output of a jerk-type circuit from the literature and an averaging operation improves the estimation.},

keywords = {Singular value decomposition;Chaotic communication;Oscilloscopes;Telecommunications;Analog circuits;Cryptography;Matrix decomposition;chaotic regime;singular value decomposition;jerk type oscillator},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{8768818,

title = {Entropy global control for a chaos based pRNG},

author = {Radu Hobincu and Octaviana Datcu and Corina Macovei},

doi = {10.1109/TSP.2019.8768818},

year  = {2019},

date = {2019-07-01},

booktitle = {2019 42nd International Conference on Telecommunications and Signal Processing (TSP)},

pages = {432-435},

abstract = {In this paper, we have attempted to resolve an important issue present in a previously proposed cryptographic pseudo-random number generator (pRNG), the issue being that for certain seeds values, the behavior of the system is not random. To solve this problem, he have added a global control system that gathers entropy and periodically alters the current internal state of the generator in order to prevent lack of randomness in the output values. The new system is empirically tested with an established randomness test battery, NIST, as well as through Monte-Carlo simulations. The results show that for almost all of the tested seeds, the output exhibits random properties.},

keywords = {NIST;Generators;Bifurcation;Entropy;Chaotic communication;Cryptography;chaotic systems;entropy control;Lyapunov exponents;pRNG;NIST randomness tests},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{9042006,

title = {Hadoop ZedBoard cluster with GZIP compression FPGA acceleration},

author = {Ovidiu Plugariu and Lucian Petrica and Radu Pirea and Radu Hobincu},

doi = {10.1109/ECAI46879.2019.9042006},

year  = {2019},

date = {2019-06-01},

booktitle = {2019 11th International Conference on Electronics, Computers and Artificial Intelligence (ECAI)},

pages = {1-5},

abstract = {This paper presents the implementation of a heterogeneous Hadoop cluster based on the Zynq ZedBoard development platform with GZIP FPGA offloading for high-speed and energy efficient computing. We have developed the first open source FPGA GZIP compressor, designed for educational and research purposes, that can reach 1 Gbps compression speed using a 125 MHz clock. The core uses only 10% of the Zynq-7020 SoC FPGA resources and is 5.7x faster than the ARM CPU which runs at 667 MHz. We implemented an eight-node Hadoop distributed cluster and performed the Wordcount and Terasort benchmarks using software and hardware GZIP compression during the Map stage. Results show an almost 2x more energy-efficient cluster when compression is done using our GZIP FPGA core than using the software compression. The performance of the Hadoop cluster is limited by the 512 MB of RAM and the low read-write speed of the SD cards which act as hard drives for each node.},

keywords = {Data centers;Program processors;Random access memory;Benchmark testing;Software;Fabrics;Distributed computing;Field programmable gate arrays;Clocks;Payloads;GZIP;FPGA;Zynq;Hadoop;Distributed Computing},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{WOS:000569996300272,

title = {Heterogenous Computing for Markov Models in Big Data},

author = {Mihaela Malita and George Vladut Popescu and Gheorghe M. Stefan},

doi = {10.1109/CSCI49370.2019.00279},

isbn = {978-1-7281-5584-5},

year  = {2019},

date = {2019-01-01},

booktitle = {2019 6TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL SCIENCE AND 

 COMPUTATIONAL INTELLIGENCE (CSCI 2019)},

pages = {1500-1505},

publisher = {IEEE},

address = {345 E 47TH ST, NEW YORK, NY 10017 USA},

abstract = {Many Big Data problems, Markov Model related included, are solved using 

 heterogenous systems: host + parallel programmable accelerator. The 

 current solutions for the accelerator part - for example, GPU used as 

 GPGPU - provide limited accelerations due to some architectural 

 constraints. The paper introduces the use of a programmable parallel 

 accelerator able to perform efficient vector and matrix operations 

 avoiding the limitations of the current systems designed using 

 ``of-theshelf'' solutions. Our main result is an architecture whose 

 actual performance is a much higher percentage from its peak performance 

 than those of the consecrated accelerators. The performance improvements 

 we offer come from the following two features: the addition of a 

 reduction network at the output of a linear array of cells and an 

 appropriate use of a serial register distributed along the same linear 

 array of cells. Thus, for a n-state Markov Model, instead of a solution 

 with the size in O(n2) and an acceleration in O(n2/logn), we offer an 

 accelerator with the size in O(n) and the acceleration in O(n).},

note = {6th Annual Conference on Computational Science and Computational 

 Intelligence (CSCI), Las Vegas, NV, DEC 05-07, 2019},

keywords = {Big Data; Markov Models; parallel architecture; accelerators;   heterogenous computing},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{WOS:000514295300023,

title = {Nano-Structural Requirements for Artificial Intelligence & Blockchain 

 Applications},

author = {Razvan Mihai and Mihaela Malita and Gheorghe M. Stefan},

editor = {G Brezeanu and ML Ciurea and D Cristea and MA Dinescu and D Dobrescu and M Dragoman and A Muller and R Muller and D Neculoiu},

doi = {10.1109/smicnd.2019.8923787},

issn = {1545-827X},

year  = {2019},

date = {2019-01-01},

booktitle = {2019 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS 2019), 42ND EDITION},

pages = {115-118},

publisher = {IEEE},

address = {345 E 47TH ST, NEW YORK, NY 10017 USA},

organization = {IEEE; IEEE Electron Devices Soc; Natl Inst Res & Dev Microtechnologies, 

 IMT Bucharest; Minist Res & Innovat; NANOTEAM S R L},

series = {International Semiconductor Conference},

abstract = {Artificial Intelligence and Blockchain are among the most demanding 

 technologies requesting tremendously powerful computation engines 

 capable to deliver fast, cheap and energy aware solutions. These 

 technologies provide the safe computational environment for making 

 intelligent decisions related to complex issues. Are presented the 

 functional aspects and the structural requirements for the emerging 

 intelligent world - the world dominated by technologically assisted 

 consensual decisions and self-enforced regulations. Finally, are 

 asserted the improvements required from the emerging nano-technologies.},

note = {42nd International Semiconductor Conference (CAS), Sinaia, ROMANIA, OCT 

 09-11, 2019},

keywords = {artificial intelligence; blockchain; parallel architecture; power aware   technology; map-reduce},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{8583863,

title = {FPGA Implementation of a Chaos Based PRNG Targetting Secret Communication},

author = {Radu Hobincu and Octaviana Datcu},

doi = {10.1109/ISETC.2018.8583863},

issn = {2475-7861},

year  = {2018},

date = {2018-11-01},

booktitle = {2018 International Symposium on Electronics and Telecommunications (ISETC)},

pages = {1-4},

abstract = {This paper describes the digital implementation of a chaos based cyptographic pseudo-random number generator using a Zynq SoC, offloading the computation to the FPGA. The implementation is based on the generalized Henon map, and it is done using fixed point 3.61 arithmetic. We will show that there is a performance improvement compared to the execution on the ARM Cortex A9 processor and that the generated random bytes are consistent with the software implementation. The generator is tested against the NIST, Dieharder and TestU01 suites.},

keywords = {Generators;Field programmable gate arrays;NIST;Chaos;Software;IP networks;Batteries;PRNG;random;chaos;Henon;FPGA;Zynq;NIST},

pubstate = {published},

tppubtype = {inproceedings}

}

@inproceedings{8604338,

title = {A Recursive Growing & Featuring Mechanism for Nanocomputing Structures},

author = {Mihaela Maliţa and Gheorghe M. Ştefan},

issn = {2327-8226},

year  = {2018},

date = {2018-07-01},

booktitle = {2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)},

pages = {1-6},

abstract = {The huge amounts of physical possibilities offered by the emerging nanotechnologies must be accompanied, beyond the uniform growing mechanisms supposed by the current serial and/or parallel extensions, by an appropriate structuring mechanism able to support efficiently the increasing functional demands. A recursive growing mechanism is proposed for the upcoming Nano-Era. The current growing mechanism involves only pure quantitative aspects. We consider as mandatory, for the very big sized systems, another mechanism which interleaves the quantitative aspects with the functional ones. Because the computational parallelism is implicit for the big sized systems, the growing mechanism must be supported also by an appropriate computational model. For the current systems we started from gates. For Nano-Era structuring mechanism we will start from cellular automata. The main difference is that for nanoarchitectures the growing mechanism and the featuring mechanism are unified in an unique recursive mechanism.},

keywords = {Computational modeling;Mathematical model;Automata;Micromechanical devices;Parallel processing;Engines;Digital systems;Parallel computing;parallel architecture;recursive functions;digital system taxonomy;functional programming},

pubstate = {published},

tppubtype = {inproceedings}

}