21.
Bratan, Costin Andrei; Tebeanu, Ana Voichita; Bobes, Gabriela; Popescu, Ionut; Iorgulescu, Gabriela; Neagu, Liliana; Apostol, Adriana; Goian, Razvan; Dascalu, Monica; Franti, Eduard; Oproiu, Ana Maria
Using Swear Words Increases the Irritability - a Study Using AI Algorithms Journal Article
In: ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, vol. 26, no. 3-4, pp. 365-374, 2023, ISSN: 1453-8245.
Abstract | Links | BibTeX | Tags: Convolutional Neural Networks; Emotion Recognition; Irritability Level; Speech Recognition; Swearing
@article{WOS:001083522800009,
title = {Using Swear Words Increases the Irritability - a Study Using AI
Algorithms},
author = {Costin Andrei Bratan and Ana Voichita Tebeanu and Gabriela Bobes and Ionut Popescu and Gabriela Iorgulescu and Liliana Neagu and Adriana Apostol and Razvan Goian and Monica Dascalu and Eduard Franti and Ana Maria Oproiu},
doi = {10.59277/ROMJIST.2023.3-4.09},
issn = {1453-8245},
year = {2023},
date = {2023-01-01},
journal = {ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY},
volume = {26},
number = {3-4},
pages = {365-374},
publisher = {EDITURA ACAD ROMANE},
address = {CALEA 13 SEPTEMBRIE NR 13, SECTOR 5, BUCURESTI 050711, ROMANIA},
abstract = {This paper presents the effects' analysis produced by the frequent use
of swearing from the perspective of irritability. The analysis was
carried out with the help of two psychological questionnaires that were
completed by the volunteers before and after the inducement of the
negative emotions and automatic recognition functions implemented by
Convolutional Neural Networks (CNN), applied for the speech signals of
two volunteer groups for whom negative emotions were induced. The CNN
architecture uses Mel-frequency cepstral coefficients (MFCCs), obtained
from the speech signal, and has 87,944 trainable parameters, the outputs
of the network being the 8 main classes of emotion detected by the
algorithm (1 neutral, 3 positive, and 4 negative). The CNN also gives
information about the negative emotion and irritability level. For the
volunteers who swore during the experiment, there is an increase of 14%
in negative emotion intensity and of 21% for the irritability level
than for the volunteers who didn't swear during the trials. The use of
this current research is the understanding that cursing causes a higher
level of irritability.},
keywords = {Convolutional Neural Networks; Emotion Recognition; Irritability Level; Speech Recognition; Swearing},
pubstate = {published},
tppubtype = {article}
}
This paper presents the effects' analysis produced by the frequent use
of swearing from the perspective of irritability. The analysis was
carried out with the help of two psychological questionnaires that were
completed by the volunteers before and after the inducement of the
negative emotions and automatic recognition functions implemented by
Convolutional Neural Networks (CNN), applied for the speech signals of
two volunteer groups for whom negative emotions were induced. The CNN
architecture uses Mel-frequency cepstral coefficients (MFCCs), obtained
from the speech signal, and has 87,944 trainable parameters, the outputs
of the network being the 8 main classes of emotion detected by the
algorithm (1 neutral, 3 positive, and 4 negative). The CNN also gives
information about the negative emotion and irritability level. For the
volunteers who swore during the experiment, there is an increase of 14%
in negative emotion intensity and of 21% for the irritability level
than for the volunteers who didn't swear during the trials. The use of
this current research is the understanding that cursing causes a higher
level of irritability.
of swearing from the perspective of irritability. The analysis was
carried out with the help of two psychological questionnaires that were
completed by the volunteers before and after the inducement of the
negative emotions and automatic recognition functions implemented by
Convolutional Neural Networks (CNN), applied for the speech signals of
two volunteer groups for whom negative emotions were induced. The CNN
architecture uses Mel-frequency cepstral coefficients (MFCCs), obtained
from the speech signal, and has 87,944 trainable parameters, the outputs
of the network being the 8 main classes of emotion detected by the
algorithm (1 neutral, 3 positive, and 4 negative). The CNN also gives
information about the negative emotion and irritability level. For the
volunteers who swore during the experiment, there is an increase of 14%
in negative emotion intensity and of 21% for the irritability level
than for the volunteers who didn't swear during the trials. The use of
this current research is the understanding that cursing causes a higher
level of irritability.
22.
Vasile, Matei-Eugen; Martoiu, Sorin; Boukadida, Nayib; Stoicea, Gabriel; Micu, Petru; Dumitru, Alexandru; Ulmamei, Andrei-Alexandru; Hobincu, Radu; Iordache, Cristina-Cerasela
Developments Regarding the Integration of FPGA RDMA into the ATLAS Readout with FELIX in High Luminosity LHC Proceedings Article
In: 2022 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), pp. 1-4, 2022, ISSN: 2577-0829.
Abstract | Links | BibTeX | Tags: Protocols;Large Hadron Collider;Throughput;Software;Hardware;Servers;Field programmable gate arrays
@inproceedings{10399028,
title = {Developments Regarding the Integration of FPGA RDMA into the ATLAS Readout with FELIX in High Luminosity LHC},
author = {Matei-Eugen Vasile and Sorin Martoiu and Nayib Boukadida and Gabriel Stoicea and Petru Micu and Alexandru Dumitru and Andrei-Alexandru Ulmamei and Radu Hobincu and Cristina-Cerasela Iordache},
doi = {10.1109/NSS/MIC44845.2022.10399028},
issn = {2577-0829},
year = {2022},
date = {2022-11-01},
booktitle = {2022 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)},
pages = {1-4},
abstract = {RDMA (Remote Direct Memory Access) is used by the ATLAS experiment at CERN in the new readout system based on FELIX (Front-End Link eXchange) for its networking layer. The FELIX system is used to interface the front-end electronics to commodity hardware in the server farm. In the current implementation of FELIX, RDMA communication is implemented using software on both ends of the RDMA links. FELIX is using RDMA through RoCE (RDMA over Converged Ethernet) to transmit data from its servers to the Software Readout Driver devices in the server farm using off-the-shelf networking equipment. As a consequence of the High Luminosity LHC upgrade, improvements in the data throughput will be needed. These improvements can be achieved by implementing RDMA support in the FELIX FPGA to simplify the path the data is taking through the readout system. This FPGA implementation of the RDMA protocol has been developed and tested. Now, a version of FELIX that uses this implementation is being proposed and demonstrated.},
keywords = {Protocols;Large Hadron Collider;Throughput;Software;Hardware;Servers;Field programmable gate arrays},
pubstate = {published},
tppubtype = {inproceedings}
}
RDMA (Remote Direct Memory Access) is used by the ATLAS experiment at CERN in the new readout system based on FELIX (Front-End Link eXchange) for its networking layer. The FELIX system is used to interface the front-end electronics to commodity hardware in the server farm. In the current implementation of FELIX, RDMA communication is implemented using software on both ends of the RDMA links. FELIX is using RDMA through RoCE (RDMA over Converged Ethernet) to transmit data from its servers to the Software Readout Driver devices in the server farm using off-the-shelf networking equipment. As a consequence of the High Luminosity LHC upgrade, improvements in the data throughput will be needed. These improvements can be achieved by implementing RDMA support in the FELIX FPGA to simplify the path the data is taking through the readout system. This FPGA implementation of the RDMA protocol has been developed and tested. Now, a version of FELIX that uses this implementation is being proposed and demonstrated.
23.
Hobincu, R.; Collaboration, The ATLAS
A detailed map of Higgs boson interactions by the ATLAS experiment ten years after the discovery Journal Article
In: Nature, vol. 607, no. 7917, pp. 52-59, 2022, ISSN: 1476-4687.
Abstract | Links | BibTeX | Tags:
@article{Aad2022,
title = {A detailed map of Higgs boson interactions by the ATLAS experiment ten years after the discovery},
author = {R. Hobincu and The ATLAS Collaboration},
url = {https://doi.org/10.1038/s41586-022-04893-w},
doi = {10.1038/s41586-022-04893-w},
issn = {1476-4687},
year = {2022},
date = {2022-07-01},
journal = {Nature},
volume = {607},
number = {7917},
pages = {52-59},
abstract = {The standard model of particle physics1–4 describes the known fundamental particles and forces that make up our Universe, with the exception of gravity. One of the central features of the standard model is a field that permeates all of space and interacts with fundamental particles5–9. The quantum excitation of this field, known as the Higgs field, manifests itself as the Higgs boson, the only fundamental particle with no spin. In 2012, a particle with properties consistent with the Higgs boson of the standard model was observed by the ATLAS and CMS experiments at the Large Hadron Collider at CERN10,11. Since then, more than 30þinspacetimes as many Higgs bosons have been recorded by the ATLAS experiment, enabling much more precise measurements and new tests of the theory. Here, on the basis of this larger dataset, we combine an unprecedented number of production and decay processes of the Higgs boson to scrutinize its interactions with elementary particles. Interactions with gluons, photons, and W and Z bosons—the carriers of the strong, electromagnetic and weak forces—are studied in detail. Interactions with three third-generation matter particles (bottom (b) and top (t) quarks, and tau leptons (τ)) are well measured and indications of interactions with a second-generation particle (muons, μ) are emerging. These tests reveal that the Higgs boson discovered ten years ago is remarkably consistent with the predictions of the theory and provide stringent constraints on many models of new phenomena beyond the standard model.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
The standard model of particle physics1–4 describes the known fundamental particles and forces that make up our Universe, with the exception of gravity. One of the central features of the standard model is a field that permeates all of space and interacts with fundamental particles5–9. The quantum excitation of this field, known as the Higgs field, manifests itself as the Higgs boson, the only fundamental particle with no spin. In 2012, a particle with properties consistent with the Higgs boson of the standard model was observed by the ATLAS and CMS experiments at the Large Hadron Collider at CERN10,11. Since then, more than 30þinspacetimes as many Higgs bosons have been recorded by the ATLAS experiment, enabling much more precise measurements and new tests of the theory. Here, on the basis of this larger dataset, we combine an unprecedented number of production and decay processes of the Higgs boson to scrutinize its interactions with elementary particles. Interactions with gluons, photons, and W and Z bosons—the carriers of the strong, electromagnetic and weak forces—are studied in detail. Interactions with three third-generation matter particles (bottom (b) and top (t) quarks, and tau leptons (τ)) are well measured and indications of interactions with a second-generation particle (muons, μ) are emerging. These tests reveal that the Higgs boson discovered ten years ago is remarkably consistent with the predictions of the theory and provide stringent constraints on many models of new phenomena beyond the standard model.
24.
Bîră, Călin; Rusu-Casandra, Alexandru
Dataset of Spatial Objects Acquired using Romania's First Ground-Based Space Tracking Radar Proceedings Article
In: 2022 14th International Conference on Communications (COMM), pp. 1-6, 2022.
Abstract | Links | BibTeX | Tags: Spaceborne radar;Surveillance;Pipelines;Receivers;Radar tracking;Spatial databases;Data models;ground-based space radar dataset;orbiting objects;space surveillance and tracking;space debris
@inproceedings{9817333,
title = {Dataset of Spatial Objects Acquired using Romania's First Ground-Based Space Tracking Radar},
author = {Călin Bîră and Alexandru Rusu-Casandra},
doi = {10.1109/COMM54429.2022.9817333},
year = {2022},
date = {2022-06-01},
booktitle = {2022 14th International Conference on Communications (COMM)},
pages = {1-6},
abstract = {Raw spatial-objects radar data is scarce and hard to obtain, obstructing simulations and making improvements to the processing pipeline rather difficult. We provide such a radar dataset of five spatial objects, acquired using the Romania's first spatial-object tracking radar, the Cheia Radar. The dataset contains the tracking of five different objects for a few minutes, using 125W transmitting power and a 2-channel 16-bit 100MSa/s ADC for the receiver end. The input conditions/TLE and the output data format are described; the digital processing pipeline used to extract relevant data is specified so that other researchers may easily use the dataset, which is available on Microsoft Sharepoint.},
keywords = {Spaceborne radar;Surveillance;Pipelines;Receivers;Radar tracking;Spatial databases;Data models;ground-based space radar dataset;orbiting objects;space surveillance and tracking;space debris},
pubstate = {published},
tppubtype = {inproceedings}
}
Raw spatial-objects radar data is scarce and hard to obtain, obstructing simulations and making improvements to the processing pipeline rather difficult. We provide such a radar dataset of five spatial objects, acquired using the Romania's first spatial-object tracking radar, the Cheia Radar. The dataset contains the tracking of five different objects for a few minutes, using 125W transmitting power and a 2-channel 16-bit 100MSa/s ADC for the receiver end. The input conditions/TLE and the output data format are described; the digital processing pipeline used to extract relevant data is specified so that other researchers may easily use the dataset, which is available on Microsoft Sharepoint.
25.
Popescu, George-Vlăduţ; Bîră, Călin
Python-Based Programming Framework for a Heterogeneous MapReduce Architecture Proceedings Article
In: 2022 14th International Conference on Communications (COMM), pp. 1-6, 2022.
Abstract | Links | BibTeX | Tags: Software packages;Linear algebra;Computer architecture;Programming;Writing;Data transfer;Libraries;Heterogeneous computing;MapReduce Accelerator;ARM-FPGA;software library;framework
@inproceedings{9817183,
title = {Python-Based Programming Framework for a Heterogeneous MapReduce Architecture},
author = {George-Vlăduţ Popescu and Călin Bîră},
doi = {10.1109/COMM54429.2022.9817183},
year = {2022},
date = {2022-06-01},
booktitle = {2022 14th International Conference on Communications (COMM)},
pages = {1-6},
abstract = {This paper presents a low-maintenance, short development-cycle programming framework (MRAFW) which allows writing and running software for a custom heterogeneous pseudo-reconfigurable computing system integrating a MapReduce Accelerator. The target system implementation is based on AMD/Xilinx's Zynq SoC hardware platform. The programming framework uses the PYNQ software package to enable access to the system resources and to manage CPU-FPGA program and data transfers. Furthermore, we provide a library of optimized low-level functions that offer support for executing some basic linear algebra operations.},
keywords = {Software packages;Linear algebra;Computer architecture;Programming;Writing;Data transfer;Libraries;Heterogeneous computing;MapReduce Accelerator;ARM-FPGA;software library;framework},
pubstate = {published},
tppubtype = {inproceedings}
}
This paper presents a low-maintenance, short development-cycle programming framework (MRAFW) which allows writing and running software for a custom heterogeneous pseudo-reconfigurable computing system integrating a MapReduce Accelerator. The target system implementation is based on AMD/Xilinx's Zynq SoC hardware platform. The programming framework uses the PYNQ software package to enable access to the system resources and to manage CPU-FPGA program and data transfers. Furthermore, we provide a library of optimized low-level functions that offer support for executing some basic linear algebra operations.
26.
Rizea, Cătălin; Bîră, Călin; Stanciu, Mihai
Robust Steganographic Algorithm based on Wavelet Transform Proceedings Article
In: 2022 14th International Conference on Communications (COMM), pp. 1-6, 2022.
Abstract | Links | BibTeX | Tags: Visualization;Steganography;Watermarking;Wavelet coefficients;steganography;robust;wavelet transform
@inproceedings{9817306,
title = {Robust Steganographic Algorithm based on Wavelet Transform},
author = {Cătălin Rizea and Călin Bîră and Mihai Stanciu},
doi = {10.1109/COMM54429.2022.9817306},
year = {2022},
date = {2022-06-01},
booktitle = {2022 14th International Conference on Communications (COMM)},
pages = {1-6},
abstract = {This paper proposes a new robust algorithm for hiding information in the visual information of images. Our robust version (RV) supports hiding data in 40×40 pixel black and white image and even after resizing and jpeg transform, around 80% of the original watermark can be recovered. Our dimension version (DV) increases the amount of data that may be hidden, up to 75% of LSB steganography but offers a high level of imperceptibility by hiding data inside the wavelet coefficients.},
keywords = {Visualization;Steganography;Watermarking;Wavelet coefficients;steganography;robust;wavelet transform},
pubstate = {published},
tppubtype = {inproceedings}
}
This paper proposes a new robust algorithm for hiding information in the visual information of images. Our robust version (RV) supports hiding data in 40×40 pixel black and white image and even after resizing and jpeg transform, around 80% of the original watermark can be recovered. Our dimension version (DV) increases the amount of data that may be hidden, up to 75% of LSB steganography but offers a high level of imperceptibility by hiding data inside the wavelet coefficients.
27.
Popescu, George-Vlăduţ; Hobincu, Radu
Open-Source, Modular, Graphical FPGA Board-Level Simulator Proceedings Article
In: 2022 14th International Conference on Communications (COMM), pp. 1-4, 2022.
Abstract | Links | BibTeX | Tags: Codes;Education;Light emitting diodes;Sequential circuits;Hardware design languages;Field programmable gate arrays;Open source software;FPGA;digital design;board-level simulator;remote teaching
@inproceedings{9817221,
title = {Open-Source, Modular, Graphical FPGA Board-Level Simulator},
author = {George-Vlăduţ Popescu and Radu Hobincu},
doi = {10.1109/COMM54429.2022.9817221},
year = {2022},
date = {2022-06-01},
booktitle = {2022 14th International Conference on Communications (COMM)},
pages = {1-4},
abstract = {This paper presents a software FPGA board simulator having Xilinx's Vivado toolchain as a backend. It offers a GUI interface to basic components such as LEDs, buttons, and switches, and may be configured to run with virtually any board without recompilation, which is very useful as a teaching/self-teaching/training tool. Both combinational and sequential circuits are supported if described in Verilog HDL. Their output is shown on the proposed GUI environment resembling various specific boards, not just on waveforms as in usual digital design simulators. The testbench can be expressed as user interaction instead of non-synthesizable code.},
keywords = {Codes;Education;Light emitting diodes;Sequential circuits;Hardware design languages;Field programmable gate arrays;Open source software;FPGA;digital design;board-level simulator;remote teaching},
pubstate = {published},
tppubtype = {inproceedings}
}
This paper presents a software FPGA board simulator having Xilinx's Vivado toolchain as a backend. It offers a GUI interface to basic components such as LEDs, buttons, and switches, and may be configured to run with virtually any board without recompilation, which is very useful as a teaching/self-teaching/training tool. Both combinational and sequential circuits are supported if described in Verilog HDL. Their output is shown on the proposed GUI environment resembling various specific boards, not just on waveforms as in usual digital design simulators. The testbench can be expressed as user interaction instead of non-synthesizable code.
28.
Ionescu, Liviu; Rusu-Casandra, Alexandru; Bira, Calin; Tatomirescu, Alexandru; Tramandan, Ionut; Scagnoli, Roberto; Istriteanu, Dan; Popa, Andrei-Edward
Development of the Romanian Radar Sensor for Space Surveillance and Tracking Activities Journal Article
In: SENSORS, vol. 22, no. 9, 2022.
Abstract | Links | BibTeX | Tags: space; surveillance; tracking; SSA; SST; LEO; radar; monostatic; debris
@article{WOS:000794693300001,
title = {Development of the Romanian Radar Sensor for Space Surveillance and
Tracking Activities},
author = {Liviu Ionescu and Alexandru Rusu-Casandra and Calin Bira and Alexandru Tatomirescu and Ionut Tramandan and Roberto Scagnoli and Dan Istriteanu and Andrei-Edward Popa},
doi = {10.3390/s22093546},
year = {2022},
date = {2022-05-01},
journal = {SENSORS},
volume = {22},
number = {9},
publisher = {MDPI},
address = {MDPI AG, Grosspeteranlage 5, CH-4052 BASEL, SWITZERLAND},
abstract = {The constant increase in the number of space objects and debris orbiting
the Earth poses risks to satellites and other spacecraft, both in orbit
and during the launching process. Therefore, the monitoring of space
hazards to assess risk and prevent collisions has become part of the
European Space Policy and requires the establishment of a dedicated
Framework for Space Surveillance and Tracking (EU SST) Support. This
article presents the CHEIA SST Radar, a new space tracking radar sensor
developed and installed in Romania with the purpose of being included in
the EU SST sensor network and of contributing to the joint database of
space objects orbiting the Earth. The paper describes the processes of
design, simulation, and implementation of the hardware and software
building blocks that make up the radar system. It emphasizes the
particular case of using an already existing system of two large
parabolic antennas requiring an innovative retrofitting design to
include them as the basis for a new quasi-monostatic radar using LFMCW
probing signals. The preliminary design was validated by extensive
simulations, and the initial operational testing carried out in December
2021 demonstrated the good performance of the radar in the measuring
range and radial speed of LEO space objects.},
keywords = {space; surveillance; tracking; SSA; SST; LEO; radar; monostatic; debris},
pubstate = {published},
tppubtype = {article}
}
The constant increase in the number of space objects and debris orbiting
the Earth poses risks to satellites and other spacecraft, both in orbit
and during the launching process. Therefore, the monitoring of space
hazards to assess risk and prevent collisions has become part of the
European Space Policy and requires the establishment of a dedicated
Framework for Space Surveillance and Tracking (EU SST) Support. This
article presents the CHEIA SST Radar, a new space tracking radar sensor
developed and installed in Romania with the purpose of being included in
the EU SST sensor network and of contributing to the joint database of
space objects orbiting the Earth. The paper describes the processes of
design, simulation, and implementation of the hardware and software
building blocks that make up the radar system. It emphasizes the
particular case of using an already existing system of two large
parabolic antennas requiring an innovative retrofitting design to
include them as the basis for a new quasi-monostatic radar using LFMCW
probing signals. The preliminary design was validated by extensive
simulations, and the initial operational testing carried out in December
2021 demonstrated the good performance of the radar in the measuring
range and radial speed of LEO space objects.
the Earth poses risks to satellites and other spacecraft, both in orbit
and during the launching process. Therefore, the monitoring of space
hazards to assess risk and prevent collisions has become part of the
European Space Policy and requires the establishment of a dedicated
Framework for Space Surveillance and Tracking (EU SST) Support. This
article presents the CHEIA SST Radar, a new space tracking radar sensor
developed and installed in Romania with the purpose of being included in
the EU SST sensor network and of contributing to the joint database of
space objects orbiting the Earth. The paper describes the processes of
design, simulation, and implementation of the hardware and software
building blocks that make up the radar system. It emphasizes the
particular case of using an already existing system of two large
parabolic antennas requiring an innovative retrofitting design to
include them as the basis for a new quasi-monostatic radar using LFMCW
probing signals. The preliminary design was validated by extensive
simulations, and the initial operational testing carried out in December
2021 demonstrated the good performance of the radar in the measuring
range and radial speed of LEO space objects.
29.
Mihalache, Serban; Burileanu, Dragos; Franti, Eduard; Dascalu, Monica; Bratan, Costin-Andrei
Lasting emotions - An investigation of short- and long-term affective content remanence in speech Journal Article
In: ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, vol. 25, no. 1, pp. 20-35, 2022, ISSN: 1453-8245.
Abstract | BibTeX | Tags: Speech emotion remanence; speech emotion recognition; machine learning; multilayer perceptrons; law enforcement
@article{WOS:000775912300002,
title = {Lasting emotions - An investigation of short- and long-term affective
content remanence in speech},
author = {Serban Mihalache and Dragos Burileanu and Eduard Franti and Monica Dascalu and Costin-Andrei Bratan},
issn = {1453-8245},
year = {2022},
date = {2022-01-01},
journal = {ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY},
volume = {25},
number = {1},
pages = {20-35},
publisher = {EDITURA ACAD ROMANE},
address = {CALEA 13 SEPTEMBRIE NR 13, SECTOR 5, BUCURESTI 050711, ROMANIA},
abstract = {Speech emotion recognition (SER) is a promising ongoing research area
with important applications for forensics and law enforcement
operations, among others. Approaches have been previously proposed to
integrate SER systems to assist in surveillance tasks, emergency
services, police investigations, or other operations, especially in the
attempt to anticipate and prevent potential criminal acts or even to
counter terrorist activities. One of the challenges presented by these
tasks consists of discerning patterns in the temporal evolution of the
affective content that would indicate suspicious behavior and warrant
further inquiry. In this work, we gain insight into these patterns and
prove that 1) if a human interaction is emotionally triggering for the
subject, then their affective response will not decay instantly, but
over a longer time period, and subsequent emotionally neutral
interactions will still be accompanied by an aroused negative affective
state (emotional remanence); and 2) if an emotionally charged event is
forthcoming for the subject, as the event draws closer, the subject will
experience higher intensity emotions and will exhibit a correspondingly
increased affective response. In order to provide a reasonable partial
proxy for the high-stakes conditions and triggers expected in real-life
scenarios, we have developed a speech dataset comprising 270 recordings
of 18 students behind on their university exams and about to attempt
them for the second or third time; thus, the upcoming exams and the
potential consequences of failing them represent the emotionally charged
event. Human evaluators labeled the recordings in terms of the
identified emotional classes (grouped into negative emotional classes
and the neutral state) and of arousal-valence affect space values.
Analyzing the annotations made by the evaluators, we prove that the
subjects' affective response is significantly higher as the emotionally
charged event approaches, and emotional remanence can be observed even
15 minutes after the initial interaction, or even after 30 minutes when
under the added influence of the event's imminence. We show that the
arousal increases (higher intensity affective response) as the event
draws closer, while the valence decreases (more negative affective
response), again supporting the second hypothesis, and suggesting that
such patterns would be relevant for the targeted applications. We
propose and implement a SER system using artificial neural networks
(ANNs) based on multilayer perceptron (MLP) models, obtaining good
performance (up to 72.7% accuracy) when training in a
speaker-independent manner, and yielding classification and regression
results consistent with those given by human evaluation, supporting the
possibility and usefulness of using machine learning (ML) systems to
monitor affective responses in order to automatically detect the
patterns associated with the behaviors relevant for forensic and law
enforcement applications and to facilitate intervention and prevention.},
keywords = {Speech emotion remanence; speech emotion recognition; machine learning; multilayer perceptrons; law enforcement},
pubstate = {published},
tppubtype = {article}
}
Speech emotion recognition (SER) is a promising ongoing research area
with important applications for forensics and law enforcement
operations, among others. Approaches have been previously proposed to
integrate SER systems to assist in surveillance tasks, emergency
services, police investigations, or other operations, especially in the
attempt to anticipate and prevent potential criminal acts or even to
counter terrorist activities. One of the challenges presented by these
tasks consists of discerning patterns in the temporal evolution of the
affective content that would indicate suspicious behavior and warrant
further inquiry. In this work, we gain insight into these patterns and
prove that 1) if a human interaction is emotionally triggering for the
subject, then their affective response will not decay instantly, but
over a longer time period, and subsequent emotionally neutral
interactions will still be accompanied by an aroused negative affective
state (emotional remanence); and 2) if an emotionally charged event is
forthcoming for the subject, as the event draws closer, the subject will
experience higher intensity emotions and will exhibit a correspondingly
increased affective response. In order to provide a reasonable partial
proxy for the high-stakes conditions and triggers expected in real-life
scenarios, we have developed a speech dataset comprising 270 recordings
of 18 students behind on their university exams and about to attempt
them for the second or third time; thus, the upcoming exams and the
potential consequences of failing them represent the emotionally charged
event. Human evaluators labeled the recordings in terms of the
identified emotional classes (grouped into negative emotional classes
and the neutral state) and of arousal-valence affect space values.
Analyzing the annotations made by the evaluators, we prove that the
subjects' affective response is significantly higher as the emotionally
charged event approaches, and emotional remanence can be observed even
15 minutes after the initial interaction, or even after 30 minutes when
under the added influence of the event's imminence. We show that the
arousal increases (higher intensity affective response) as the event
draws closer, while the valence decreases (more negative affective
response), again supporting the second hypothesis, and suggesting that
such patterns would be relevant for the targeted applications. We
propose and implement a SER system using artificial neural networks
(ANNs) based on multilayer perceptron (MLP) models, obtaining good
performance (up to 72.7% accuracy) when training in a
speaker-independent manner, and yielding classification and regression
results consistent with those given by human evaluation, supporting the
possibility and usefulness of using machine learning (ML) systems to
monitor affective responses in order to automatically detect the
patterns associated with the behaviors relevant for forensic and law
enforcement applications and to facilitate intervention and prevention.
with important applications for forensics and law enforcement
operations, among others. Approaches have been previously proposed to
integrate SER systems to assist in surveillance tasks, emergency
services, police investigations, or other operations, especially in the
attempt to anticipate and prevent potential criminal acts or even to
counter terrorist activities. One of the challenges presented by these
tasks consists of discerning patterns in the temporal evolution of the
affective content that would indicate suspicious behavior and warrant
further inquiry. In this work, we gain insight into these patterns and
prove that 1) if a human interaction is emotionally triggering for the
subject, then their affective response will not decay instantly, but
over a longer time period, and subsequent emotionally neutral
interactions will still be accompanied by an aroused negative affective
state (emotional remanence); and 2) if an emotionally charged event is
forthcoming for the subject, as the event draws closer, the subject will
experience higher intensity emotions and will exhibit a correspondingly
increased affective response. In order to provide a reasonable partial
proxy for the high-stakes conditions and triggers expected in real-life
scenarios, we have developed a speech dataset comprising 270 recordings
of 18 students behind on their university exams and about to attempt
them for the second or third time; thus, the upcoming exams and the
potential consequences of failing them represent the emotionally charged
event. Human evaluators labeled the recordings in terms of the
identified emotional classes (grouped into negative emotional classes
and the neutral state) and of arousal-valence affect space values.
Analyzing the annotations made by the evaluators, we prove that the
subjects' affective response is significantly higher as the emotionally
charged event approaches, and emotional remanence can be observed even
15 minutes after the initial interaction, or even after 30 minutes when
under the added influence of the event's imminence. We show that the
arousal increases (higher intensity affective response) as the event
draws closer, while the valence decreases (more negative affective
response), again supporting the second hypothesis, and suggesting that
such patterns would be relevant for the targeted applications. We
propose and implement a SER system using artificial neural networks
(ANNs) based on multilayer perceptron (MLP) models, obtaining good
performance (up to 72.7% accuracy) when training in a
speaker-independent manner, and yielding classification and regression
results consistent with those given by human evaluation, supporting the
possibility and usefulness of using machine learning (ML) systems to
monitor affective responses in order to automatically detect the
patterns associated with the behaviors relevant for forensic and law
enforcement applications and to facilitate intervention and prevention.
30.
Ștefan, Gheorghe M.
Let's consider Moore's law in its entirety Proceedings Article
In: 2021 International Semiconductor Conference (CAS), pp. 3-10, 2021, ISSN: 2377-0678.
Abstract | Links | BibTeX | Tags: Semiconductor device modeling;Computers;Computational modeling;Moore's Law;Parallel processing;Integrated circuit modeling;Moore’s Law;intense computation;accelerators;parallelism;mathematical model of parallel computing;abstract model for parallelism
@inproceedings{9604143,
title = {Let's consider Moore's law in its entirety},
author = {Gheorghe M. Ștefan},
doi = {10.1109/CAS52836.2021.9604143},
issn = {2377-0678},
year = {2021},
date = {2021-10-01},
booktitle = {2021 International Semiconductor Conference (CAS)},
pages = {3-10},
abstract = {Gordon Moore's predictions refer, in addition to the resolution at which we can make the devices, also to the size of the chips and to the "circuit cleverness". Considering Moore's law in all its aspects offers a more complex perspective on the current evolution of the field of integrated circuits. Computers, as a General-Purpose Technology, tend to be replaced by various types of accelerators. A possible solution that we present is based on parallelism supported by the recursive abstract model that we propose starting from the model of partially recursive functions of Stephen Kleene.},
keywords = {Semiconductor device modeling;Computers;Computational modeling;Moore's Law;Parallel processing;Integrated circuit modeling;Moore’s Law;intense computation;accelerators;parallelism;mathematical model of parallel computing;abstract model for parallelism},
pubstate = {published},
tppubtype = {inproceedings}
}
Gordon Moore's predictions refer, in addition to the resolution at which we can make the devices, also to the size of the chips and to the "circuit cleverness". Considering Moore's law in all its aspects offers a more complex perspective on the current evolution of the field of integrated circuits. Computers, as a General-Purpose Technology, tend to be replaced by various types of accelerators. A possible solution that we present is based on parallelism supported by the recursive abstract model that we propose starting from the model of partially recursive functions of Stephen Kleene.
31.
Ștefan, Gheorghe; Alexandru, Dinu
Controlling hardware design behavior using Python based machine learning algorithms Proceedings Article
In: 2021 16th International Conference on Engineering of Modern Electric Systems (EMES), pp. 1-4, 2021.
Abstract | Links | BibTeX | Tags: Training;Analytical models;Reinforcement learning;Tools;Hardware;Software;Data models;reinforcement learning;functional verification;hardware;automation
@inproceedings{9484105,
title = {Controlling hardware design behavior using Python based machine learning algorithms},
author = {Gheorghe Ștefan and Dinu Alexandru},
doi = {10.1109/EMES52337.2021.9484105},
year = {2021},
date = {2021-06-01},
booktitle = {2021 16th International Conference on Engineering of Modern Electric Systems (EMES)},
pages = {1-4},
abstract = {Hardware design and software programming. Two powerful worlds, where functionality is described by coding complex functions which will operate either in silicon or in a processor logic. Hardware provides accurate implementation of application needs at highest speeds. Software provides the welcome flexibility when the system needs an update. And the combination of the two approaches, well represented in industry by System-on-chip[1], leads to the powerful devices which are more and more present in our lives. But the well co-operation between hardware and software bring its advantages even from design phase. Software helps a lot hardware development, through powerful tools used at design, verification, synthesis and all other design steps. Software development is accelerated by hardware platforms which make possible intensive testing and scenarios creation for validation of new program releases. This paper exploits the opportunity of using software in hardware development. It demonstrates, both graphically and numerically, that desired verification scenarios can be faster reached by integrating a powerful machine learning technique in design verification: reinforcement learning.},
keywords = {Training;Analytical models;Reinforcement learning;Tools;Hardware;Software;Data models;reinforcement learning;functional verification;hardware;automation},
pubstate = {published},
tppubtype = {inproceedings}
}
Hardware design and software programming. Two powerful worlds, where functionality is described by coding complex functions which will operate either in silicon or in a processor logic. Hardware provides accurate implementation of application needs at highest speeds. Software provides the welcome flexibility when the system needs an update. And the combination of the two approaches, well represented in industry by System-on-chip[1], leads to the powerful devices which are more and more present in our lives. But the well co-operation between hardware and software bring its advantages even from design phase. Software helps a lot hardware development, through powerful tools used at design, verification, synthesis and all other design steps. Software development is accelerated by hardware platforms which make possible intensive testing and scenarios creation for validation of new program releases. This paper exploits the opportunity of using software in hardware development. It demonstrates, both graphically and numerically, that desired verification scenarios can be faster reached by integrating a powerful machine learning technique in design verification: reinforcement learning.
32.
Vizitiu, Cristian; Bira, Calin; Dinculescu, Adrian; Nistorescu, Alexandru; Marin, Mihaela
In: SENSORS, vol. 21, no. 5, 2021.
Abstract | Links | BibTeX | Tags: e-Health; internet of things (IoT); elders; independent living; active and assisted living (AAL); systems engineering; biometric sensors; arduino; noncommunicable diseases (NCDs); choice reaction time (CRT)
@article{WOS:000628546300001,
title = {Exhaustive Description of the System Architecture and Prototype
Implementation of an IoT-Based eHealth Biometric Monitoring System for
Elders in Independent Living},
author = {Cristian Vizitiu and Calin Bira and Adrian Dinculescu and Alexandru Nistorescu and Mihaela Marin},
doi = {10.3390/s21051837},
year = {2021},
date = {2021-03-01},
journal = {SENSORS},
volume = {21},
number = {5},
publisher = {MDPI},
address = {ST ALBAN-ANLAGE 66, CH-4052 BASEL, SWITZERLAND},
abstract = {In this paper, we present an exhaustive description of an extensible
e-Health Internet-connected embedded system, which allows the
measurement of three biometric parameters: pulse rate, oxygen saturation
and temperature, via several wired and wireless sensors residing to the
realm of Noncommunicable Diseases (NCDs) and cognitive assessment
through Choice Reaction Time (CRT) analysis. The hardware used is based
on ATMEGA AVR + MySignals Hardware printed circuit board (Hardware PCB),
but with multiple upgrades (including porting from ATMEGA328P to
ATMEGA2560). Multiple software improvements were made (by writing
high-level device drivers, text-mode and graphic-mode display driver)
for increasing functionality, portability, speed, and latency. A
top-level embedded application was developed and benchmarked. A custom
wireless AT command firmware was developed, based on ESP8266 firmware to
allow AP-mode configuration and single-command JavaScript Object
Notation (JSON) data-packet pushing towards the cloud platform. All
software is available in a git repository, including the measurement
results. The proposed eHealth system provides with specific NCDs and
cognitive views fostering the potential to exploit correlations between
physiological and cognitive data and to generate predictive analysis in
the field of eldercare.},
keywords = {e-Health; internet of things (IoT); elders; independent living; active and assisted living (AAL); systems engineering; biometric sensors; arduino; noncommunicable diseases (NCDs); choice reaction time (CRT)},
pubstate = {published},
tppubtype = {article}
}
In this paper, we present an exhaustive description of an extensible
e-Health Internet-connected embedded system, which allows the
measurement of three biometric parameters: pulse rate, oxygen saturation
and temperature, via several wired and wireless sensors residing to the
realm of Noncommunicable Diseases (NCDs) and cognitive assessment
through Choice Reaction Time (CRT) analysis. The hardware used is based
on ATMEGA AVR + MySignals Hardware printed circuit board (Hardware PCB),
but with multiple upgrades (including porting from ATMEGA328P to
ATMEGA2560). Multiple software improvements were made (by writing
high-level device drivers, text-mode and graphic-mode display driver)
for increasing functionality, portability, speed, and latency. A
top-level embedded application was developed and benchmarked. A custom
wireless AT command firmware was developed, based on ESP8266 firmware to
allow AP-mode configuration and single-command JavaScript Object
Notation (JSON) data-packet pushing towards the cloud platform. All
software is available in a git repository, including the measurement
results. The proposed eHealth system provides with specific NCDs and
cognitive views fostering the potential to exploit correlations between
physiological and cognitive data and to generate predictive analysis in
the field of eldercare.
e-Health Internet-connected embedded system, which allows the
measurement of three biometric parameters: pulse rate, oxygen saturation
and temperature, via several wired and wireless sensors residing to the
realm of Noncommunicable Diseases (NCDs) and cognitive assessment
through Choice Reaction Time (CRT) analysis. The hardware used is based
on ATMEGA AVR + MySignals Hardware printed circuit board (Hardware PCB),
but with multiple upgrades (including porting from ATMEGA328P to
ATMEGA2560). Multiple software improvements were made (by writing
high-level device drivers, text-mode and graphic-mode display driver)
for increasing functionality, portability, speed, and latency. A
top-level embedded application was developed and benchmarked. A custom
wireless AT command firmware was developed, based on ESP8266 firmware to
allow AP-mode configuration and single-command JavaScript Object
Notation (JSON) data-packet pushing towards the cloud platform. All
software is available in a git repository, including the measurement
results. The proposed eHealth system provides with specific NCDs and
cognitive views fostering the potential to exploit correlations between
physiological and cognitive data and to generate predictive analysis in
the field of eldercare.
33.
Gindac, Andrei; Popa, Andrei-Edward; Ulmamei, Andrei-Alexandru; Bira, Calin
Open-source SoC-based Off-the-shelf Industrial-Grade Low-Cost Logic Analyzer Journal Article
In: ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, vol. 24, no. 1, pp. 117-126, 2021, ISSN: 1453-8245.
Abstract | BibTeX | Tags: SoC; FPGA; HLS; HDL; many channels; logic analyzer
@article{WOS:000636230100007,
title = {Open-source SoC-based Off-the-shelf Industrial-Grade Low-Cost Logic
Analyzer},
author = {Andrei Gindac and Andrei-Edward Popa and Andrei-Alexandru Ulmamei and Calin Bira},
issn = {1453-8245},
year = {2021},
date = {2021-01-01},
journal = {ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY},
volume = {24},
number = {1},
pages = {117-126},
publisher = {EDITURA ACAD ROMANE},
address = {CALEA 13 SEPTEMBRIE NR 13, SECTOR 5, BUCURESTI 050711, ROMANIA},
abstract = {This paper proposes a solution for back-to-back 200+ MHz 150-channel
data acquisition based on Xilinxs Zynq-7000 family (dual-core ARM +
Artix-class FPGA) with Linux Ubuntu rootfs and PYNQ software framework
and application running in Jupyter notebook. A comparison is made
between High Level Synthesis (HLS) and Hardware Description Language
(HDL) versions of the device (performance, power consumption). It
distinguishes itself from the state of art by providing a very good
(MSa/s * channel) / USD value, in addition to large amounts of sample
storage.},
keywords = {SoC; FPGA; HLS; HDL; many channels; logic analyzer},
pubstate = {published},
tppubtype = {article}
}
This paper proposes a solution for back-to-back 200+ MHz 150-channel
data acquisition based on Xilinxs Zynq-7000 family (dual-core ARM +
Artix-class FPGA) with Linux Ubuntu rootfs and PYNQ software framework
and application running in Jupyter notebook. A comparison is made
between High Level Synthesis (HLS) and Hardware Description Language
(HDL) versions of the device (performance, power consumption). It
distinguishes itself from the state of art by providing a very good
(MSa/s * channel) / USD value, in addition to large amounts of sample
storage.
data acquisition based on Xilinxs Zynq-7000 family (dual-core ARM +
Artix-class FPGA) with Linux Ubuntu rootfs and PYNQ software framework
and application running in Jupyter notebook. A comparison is made
between High Level Synthesis (HLS) and Hardware Description Language
(HDL) versions of the device (performance, power consumption). It
distinguishes itself from the state of art by providing a very good
(MSa/s * channel) / USD value, in addition to large amounts of sample
storage.
34.
Stefan, Gheorghe M.
Let's consider Moore's law in its entirety Proceedings Article
In: 2021 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), pp. 3-10, IEEE; IEEE Electron Devices Soc IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2021, ISSN: 1545-827X, (44th International Semiconductor Conference (CAS), ELECTR NETWORK, OCT 06-08, 2021).
Abstract | Links | BibTeX | Tags: Moore's Law; intense computation; accelerators; parallelism; mathematical model of parallel computing; abstract model for parallelism
@inproceedings{WOS:000853482700001,
title = {Let's consider Moore's law in its entirety},
author = {Gheorghe M. Stefan},
doi = {10.1109/CAS52836.2021.9604143},
issn = {1545-827X},
year = {2021},
date = {2021-01-01},
booktitle = {2021 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS)},
pages = {3-10},
publisher = {IEEE},
address = {345 E 47TH ST, NEW YORK, NY 10017 USA},
organization = {IEEE; IEEE Electron Devices Soc},
series = {International Semiconductor Conference},
abstract = {Gordon Moore's predictions refer, in addition to the resolution at which
we can make the devices, also to the size of the chips and to the
``circuit cleverness''. Considering Moore's law in all its aspects
offers a more complex perspective on the current evolution of the field
of integrated circuits. Computers, as a General-Purpose Technology, tend
to be replaced by various types of accelerators. A possible solution
that we present is based on parallelism supported by the recursive
abstract model that we propose starting from the model of partially
recursive functions of Stephen Kleene.},
note = {44th International Semiconductor Conference (CAS), ELECTR NETWORK, OCT
06-08, 2021},
keywords = {Moore's Law; intense computation; accelerators; parallelism; mathematical model of parallel computing; abstract model for parallelism},
pubstate = {published},
tppubtype = {inproceedings}
}
Gordon Moore's predictions refer, in addition to the resolution at which
we can make the devices, also to the size of the chips and to the
``circuit cleverness''. Considering Moore's law in all its aspects
offers a more complex perspective on the current evolution of the field
of integrated circuits. Computers, as a General-Purpose Technology, tend
to be replaced by various types of accelerators. A possible solution
that we present is based on parallelism supported by the recursive
abstract model that we propose starting from the model of partially
recursive functions of Stephen Kleene.
we can make the devices, also to the size of the chips and to the
``circuit cleverness''. Considering Moore's law in all its aspects
offers a more complex perspective on the current evolution of the field
of integrated circuits. Computers, as a General-Purpose Technology, tend
to be replaced by various types of accelerators. A possible solution
that we present is based on parallelism supported by the recursive
abstract model that we propose starting from the model of partially
recursive functions of Stephen Kleene.
35.
Stefan, Gheorghe M.
Pseudo-Reconfigurable Computing Journal Article
In: ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, vol. 24, no. 4, SI, pp. 366-383, 2021, ISSN: 1453-8245.
@article{WOS:000731880700003,
title = {Pseudo-Reconfigurable Computing},
author = {Gheorghe M. Stefan},
issn = {1453-8245},
year = {2021},
date = {2021-01-01},
journal = {ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY},
volume = {24},
number = {4, SI},
pages = {366-383},
publisher = {EDITURA ACAD ROMANE},
address = {CALEA 13 SEPTEMBRIE NR 13, SECTOR 5, BUCURESTI 050711, ROMANIA},
abstract = {The pseudo-reconfigurable computing we propose is an implementation of
heterogeneous computing in the form of a compromise between the
realization of accelerators as circuits through reconfiguration
techniques using FPGAs and the realization of accelerators as parallel
computing structures made in ASIC technology. The proposed solution is
implementable in FPGA in the form of a programmable structure that is
parameterizable and configurable. The programmable accelerator is a
cellular parallel engine with a structure and architecture that
efficiently covers most of the parallel computing patterns. The
structural and architectural aspects of the proposed system are
introduced based on Stephen Kleene's Partial Recursive Function Model,
and evaluated using: (1) Functional Forms introduced by John Backus, (2)
`dwarfs'' listed in the Berkeley's View of Parallel Landscape, and
last but not least (3) patterns already imposed in the practice of
parallel computing.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
The pseudo-reconfigurable computing we propose is an implementation of
heterogeneous computing in the form of a compromise between the
realization of accelerators as circuits through reconfiguration
techniques using FPGAs and the realization of accelerators as parallel
computing structures made in ASIC technology. The proposed solution is
implementable in FPGA in the form of a programmable structure that is
parameterizable and configurable. The programmable accelerator is a
cellular parallel engine with a structure and architecture that
efficiently covers most of the parallel computing patterns. The
structural and architectural aspects of the proposed system are
introduced based on Stephen Kleene's Partial Recursive Function Model,
and evaluated using: (1) Functional Forms introduced by John Backus, (2)
`dwarfs'' listed in the Berkeley's View of Parallel Landscape, and
last but not least (3) patterns already imposed in the practice of
parallel computing.
heterogeneous computing in the form of a compromise between the
realization of accelerators as circuits through reconfiguration
techniques using FPGAs and the realization of accelerators as parallel
computing structures made in ASIC technology. The proposed solution is
implementable in FPGA in the form of a programmable structure that is
parameterizable and configurable. The programmable accelerator is a
cellular parallel engine with a structure and architecture that
efficiently covers most of the parallel computing patterns. The
structural and architectural aspects of the proposed system are
introduced based on Stephen Kleene's Partial Recursive Function Model,
and evaluated using: (1) Functional Forms introduced by John Backus, (2)
`dwarfs'' listed in the Berkeley's View of Parallel Landscape, and
last but not least (3) patterns already imposed in the practice of
parallel computing.
36.
Dinu, Alexandru; Gheorghe, Stefan; Danciu, Gabriel Mihail; Ogrutan, Petre Lucian
Debugging FPGA projects using artificial intelligence Journal Article
In: ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, vol. 24, no. 3, pp. 299-320, 2021, ISSN: 1453-8245.
Abstract | BibTeX | Tags: data mining and analysis; FPGA; machine learning; deep learning; reference model; neural network configuration
@article{WOS:000704174600003,
title = {Debugging FPGA projects using artificial intelligence},
author = {Alexandru Dinu and Stefan Gheorghe and Gabriel Mihail Danciu and Petre Lucian Ogrutan},
issn = {1453-8245},
year = {2021},
date = {2021-01-01},
journal = {ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY},
volume = {24},
number = {3},
pages = {299-320},
publisher = {EDITURA ACAD ROMANE},
address = {CALEA 13 SEPTEMBRIE NR 13, SECTOR 5, BUCURESTI 050711, ROMANIA},
abstract = {Debugging digital designs implemented into FPGA devices is a challenging
task. As opposite to simulation, simultaneous access to all input and
output signals is not possible. The main obstacles in the debugging
process are a limited number of input/output ports of FPGAs and the
transfer of information from a digital device to an external data
processor. However, debugging a digital design requests analysis of many
combinations of inputs and outputs of a module to assess if these are
well correlated and if their operation matches device specifications.
The current work of the research team consisted of designing an
end-to-end flow of data processing that fulfills the aim of debugging
digital designs (particularly in this work, FPGA devices are
considered). Firstly, a data generator based on majority voting idea was
created using RTL languages. After checking its behavior using
simulation, it has been downloaded into the FPGA fabric of a Spartan 3E
board. The data generated from this reconfigurable device was acquired
through the UART protocol, using an FT232R adapter. It was preprocessed
to reconstruct the fields of each data sample and to remove transmission
errors. The team analyzed the distribution of the obtained values and
adjusted the data to achieve a uniform distribution. The team used the
data to train both machine learning and deep learning models to create a
golden reference model which accurately reflects the main functionality
of the DUT: executing the majority vote operation over three pairs of
numbers. Finally, the team presented how to use the resulting reference
model to debug digital systems.},
keywords = {data mining and analysis; FPGA; machine learning; deep learning; reference model; neural network configuration},
pubstate = {published},
tppubtype = {article}
}
Debugging digital designs implemented into FPGA devices is a challenging
task. As opposite to simulation, simultaneous access to all input and
output signals is not possible. The main obstacles in the debugging
process are a limited number of input/output ports of FPGAs and the
transfer of information from a digital device to an external data
processor. However, debugging a digital design requests analysis of many
combinations of inputs and outputs of a module to assess if these are
well correlated and if their operation matches device specifications.
The current work of the research team consisted of designing an
end-to-end flow of data processing that fulfills the aim of debugging
digital designs (particularly in this work, FPGA devices are
considered). Firstly, a data generator based on majority voting idea was
created using RTL languages. After checking its behavior using
simulation, it has been downloaded into the FPGA fabric of a Spartan 3E
board. The data generated from this reconfigurable device was acquired
through the UART protocol, using an FT232R adapter. It was preprocessed
to reconstruct the fields of each data sample and to remove transmission
errors. The team analyzed the distribution of the obtained values and
adjusted the data to achieve a uniform distribution. The team used the
data to train both machine learning and deep learning models to create a
golden reference model which accurately reflects the main functionality
of the DUT: executing the majority vote operation over three pairs of
numbers. Finally, the team presented how to use the resulting reference
model to debug digital systems.
task. As opposite to simulation, simultaneous access to all input and
output signals is not possible. The main obstacles in the debugging
process are a limited number of input/output ports of FPGAs and the
transfer of information from a digital device to an external data
processor. However, debugging a digital design requests analysis of many
combinations of inputs and outputs of a module to assess if these are
well correlated and if their operation matches device specifications.
The current work of the research team consisted of designing an
end-to-end flow of data processing that fulfills the aim of debugging
digital designs (particularly in this work, FPGA devices are
considered). Firstly, a data generator based on majority voting idea was
created using RTL languages. After checking its behavior using
simulation, it has been downloaded into the FPGA fabric of a Spartan 3E
board. The data generated from this reconfigurable device was acquired
through the UART protocol, using an FT232R adapter. It was preprocessed
to reconstruct the fields of each data sample and to remove transmission
errors. The team analyzed the distribution of the obtained values and
adjusted the data to achieve a uniform distribution. The team used the
data to train both machine learning and deep learning models to create a
golden reference model which accurately reflects the main functionality
of the DUT: executing the majority vote operation over three pairs of
numbers. Finally, the team presented how to use the resulting reference
model to debug digital systems.
37.
Bratan, Costin Andrei; Gheorghe, Mirela; Ispas, Ioan; Franti, Eduard; Dascalu, Monica; Stoicescu, Silvia Maria; Rosca, Ioana; Gherghiceanu, Florentina; Dumitrache, Doina; Nastase, Leonard
Dunstan Baby Language Classification with CNN Proceedings Article
In: 2021 INTERNATIONAL CONFERENCE ON SPEECH TECHNOLOGY AND HUMAN-COMPUTER DIALOGUE (SPED), pp. 167-171, IEEE; Univ Politehnica Bucuresti; ETTI; AMPUS; IASI, Inst Comp Sci; Acad Romana; EURASIP IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2021, ISBN: 978-1-6654-2786-9, (11th International Conference on Speech Technology and Human-Computer Dialogue (SpeD), Bucharest, ROMANIA, OCT 13-15, 2021).
Abstract | Links | BibTeX | Tags: Dunstan baby language; convolutional neural network; infant cry classification
@inproceedings{WOS:000786794700030,
title = {Dunstan Baby Language Classification with CNN},
author = {Costin Andrei Bratan and Mirela Gheorghe and Ioan Ispas and Eduard Franti and Monica Dascalu and Silvia Maria Stoicescu and Ioana Rosca and Florentina Gherghiceanu and Doina Dumitrache and Leonard Nastase},
doi = {10.1109/SpeD53181.2021.9587374},
isbn = {978-1-6654-2786-9},
year = {2021},
date = {2021-01-01},
booktitle = {2021 INTERNATIONAL CONFERENCE ON SPEECH TECHNOLOGY AND HUMAN-COMPUTER
DIALOGUE (SPED)},
pages = {167-171},
publisher = {IEEE},
address = {345 E 47TH ST, NEW YORK, NY 10017 USA},
organization = {IEEE; Univ Politehnica Bucuresti; ETTI; AMPUS; IASI, Inst Comp Sci; Acad
Romana; EURASIP},
abstract = {Several methods were reported in the scientific literature for the
classification of the infant cries, in order to automatically detect the
need behind their tears and help the parents and caretakers. In the same
scope, this paper has an original approach in which the sounds that
precede the cry are used. Such sounds can be considered primitive words
and are classified according to the ``Dunstan Baby Language''. The
paper verifies the universal baby language hypothesis starting from the
research reported in a previous article. A CNN architecture trained with
recordings of babies from Australia was used for classifying the audio
material coming from Romanian babies. It was an attempt to see what
happens should the participants belong to a different cultural
landscape. The database loaded with the sounds made by Romanian babies
was labelled by doctors in the maternity hospitals and two Dunstan
experts, separately. Finally, the results of the CNN automatic
classification were compared to those obtained by the Dunstan coaches.
The conclusions have proved that Dunstan language is universal.},
note = {11th International Conference on Speech Technology and Human-Computer
Dialogue (SpeD), Bucharest, ROMANIA, OCT 13-15, 2021},
keywords = {Dunstan baby language; convolutional neural network; infant cry classification},
pubstate = {published},
tppubtype = {inproceedings}
}
Several methods were reported in the scientific literature for the
classification of the infant cries, in order to automatically detect the
need behind their tears and help the parents and caretakers. In the same
scope, this paper has an original approach in which the sounds that
precede the cry are used. Such sounds can be considered primitive words
and are classified according to the ``Dunstan Baby Language''. The
paper verifies the universal baby language hypothesis starting from the
research reported in a previous article. A CNN architecture trained with
recordings of babies from Australia was used for classifying the audio
material coming from Romanian babies. It was an attempt to see what
happens should the participants belong to a different cultural
landscape. The database loaded with the sounds made by Romanian babies
was labelled by doctors in the maternity hospitals and two Dunstan
experts, separately. Finally, the results of the CNN automatic
classification were compared to those obtained by the Dunstan coaches.
The conclusions have proved that Dunstan language is universal.
classification of the infant cries, in order to automatically detect the
need behind their tears and help the parents and caretakers. In the same
scope, this paper has an original approach in which the sounds that
precede the cry are used. Such sounds can be considered primitive words
and are classified according to the ``Dunstan Baby Language''. The
paper verifies the universal baby language hypothesis starting from the
research reported in a previous article. A CNN architecture trained with
recordings of babies from Australia was used for classifying the audio
material coming from Romanian babies. It was an attempt to see what
happens should the participants belong to a different cultural
landscape. The database loaded with the sounds made by Romanian babies
was labelled by doctors in the maternity hospitals and two Dunstan
experts, separately. Finally, the results of the CNN automatic
classification were compared to those obtained by the Dunstan coaches.
The conclusions have proved that Dunstan language is universal.
38.
Maliţa, Mihaela; Popescu, George Vlăduţ; Ştefan, Gheorghe M.
Pseudo-Reconfigurable Heterogeneous Solution for Accelerating Spectral Clustering Proceedings Article
In: 2020 IEEE International Conference on Big Data (Big Data), pp. 5138-5145, 2020.
Abstract | Links | BibTeX | Tags: Clustering algorithms;Machine learning;Linear algebra;Heterogeneous networks;Registers;Acceleration;Field programmable gate arrays;Spectral clustering;parallel algorithm;parallel computing;accelerator;heterogeneous computing;pseudo-reconfigurable computing
@inproceedings{9378150,
title = {Pseudo-Reconfigurable Heterogeneous Solution for Accelerating Spectral Clustering},
author = {Mihaela Maliţa and George Vlăduţ Popescu and Gheorghe M. Ştefan},
doi = {10.1109/BigData50022.2020.9378150},
year = {2020},
date = {2020-12-01},
booktitle = {2020 IEEE International Conference on Big Data (Big Data)},
pages = {5138-5145},
abstract = {Spectral clustering is a Machine Learning technique intensively used in Big Data applications. It makes extensive use of linear algebra. This article introduces the concept of MapReduce Accelerator (MRA) as the reconfigurable part of a heterogeneous computing system. Although the accelerator we propose is a general purpose one, it has some specific features related to the targeted application. This is possible due to the pseudo-reconfigurable environment which deploys in FPGA a parameterizable programmable accelerator. The main specific characteristics of the accelerator are proposed as a result of the analysis performed on the spectral clustering algorithms. The architecture is described and the spectral clustering algorithms are evaluated. The proposed solution is compared, in terms of computing performance and energy consumption, with other solutions published in the literature. The increase in computing performance is accompanied by a 3-5 times reduction in energy consumed. The accelerator is a linear array of cells controlled by a sequencer loop closed through a reduction network. Each cell is a simple, accumulator-based execution unit with a big two-port register file. The reduction network is a log-depth pipelined circuit performing few reduction functions such as add, min, max. The experimental system is a PYNQ-Z2 board equipped with Zinq 7020 SoC; it is used to implement and evaluate the acceleration provided by an 128-cell MRA.},
keywords = {Clustering algorithms;Machine learning;Linear algebra;Heterogeneous networks;Registers;Acceleration;Field programmable gate arrays;Spectral clustering;parallel algorithm;parallel computing;accelerator;heterogeneous computing;pseudo-reconfigurable computing},
pubstate = {published},
tppubtype = {inproceedings}
}
Spectral clustering is a Machine Learning technique intensively used in Big Data applications. It makes extensive use of linear algebra. This article introduces the concept of MapReduce Accelerator (MRA) as the reconfigurable part of a heterogeneous computing system. Although the accelerator we propose is a general purpose one, it has some specific features related to the targeted application. This is possible due to the pseudo-reconfigurable environment which deploys in FPGA a parameterizable programmable accelerator. The main specific characteristics of the accelerator are proposed as a result of the analysis performed on the spectral clustering algorithms. The architecture is described and the spectral clustering algorithms are evaluated. The proposed solution is compared, in terms of computing performance and energy consumption, with other solutions published in the literature. The increase in computing performance is accompanied by a 3-5 times reduction in energy consumed. The accelerator is a linear array of cells controlled by a sequencer loop closed through a reduction network. Each cell is a simple, accumulator-based execution unit with a big two-port register file. The reduction network is a log-depth pipelined circuit performing few reduction functions such as add, min, max. The experimental system is a PYNQ-Z2 board equipped with Zinq 7020 SoC; it is used to implement and evaluate the acceleration provided by an 128-cell MRA.
39.
Vizitiu, Cristian; Bîră, Călin; Dinculescu, Adrian; Mandu, Mihai; Nistorescu, Alexandru; Marin, Mihaela
eHealth Perspective Co-designed and Implemented with Romanian Elders for Independent Living Proceedings Article
In: 2020 International Conference on e-Health and Bioengineering (EHB), pp. 1-4, 2020, ISSN: 2575-5145.
Abstract | Links | BibTeX | Tags: Electronic healthcare;Sensors;Biometrics (access control);Cloud computing;Biosensors;Software;Wireless fidelity;eHealth;elders;biometric information;Systems Engineering (SE);Active and Assisted Living Programme (AAL)
@inproceedings{9279884,
title = {eHealth Perspective Co-designed and Implemented with Romanian Elders for Independent Living},
author = {Cristian Vizitiu and Călin Bîră and Adrian Dinculescu and Mihai Mandu and Alexandru Nistorescu and Mihaela Marin},
doi = {10.1109/EHB50910.2020.9279884},
issn = {2575-5145},
year = {2020},
date = {2020-10-01},
booktitle = {2020 International Conference on e-Health and Bioengineering (EHB)},
pages = {1-4},
abstract = {Given the context of 20% increased number of individuals over 60 years till 2030 and further, there is emerging a real need to support elderly people in independent living while eHealth technologies proved to be promising solutions in this role. The paper presents an eHealth solution via co-design and Proof of Concept (PoC) perspective on Romanian elders, demarches led within the international Active and Assisted Living (AAL) Programme endorsing “smart solutions for ageing well” vision. The eHealth solution, based on open source hardware for interoperability and scalability, supports elders to collect biometric information at home and further provides this info to the corresponding caregivers/volunteers when needed in order to take actions accordingly in proper time. The eHealth system, planned according to Systems Engineering methodology, took in consideration Romanian end-user requirements whose verifications were performed via a PoC implementation. Subsequently the concept will become more comprehensive after several co-design sessions planned to be performed also in Hungary and Italy, partner countries in AAL project consortium.},
keywords = {Electronic healthcare;Sensors;Biometrics (access control);Cloud computing;Biosensors;Software;Wireless fidelity;eHealth;elders;biometric information;Systems Engineering (SE);Active and Assisted Living Programme (AAL)},
pubstate = {published},
tppubtype = {inproceedings}
}
Given the context of 20% increased number of individuals over 60 years till 2030 and further, there is emerging a real need to support elderly people in independent living while eHealth technologies proved to be promising solutions in this role. The paper presents an eHealth solution via co-design and Proof of Concept (PoC) perspective on Romanian elders, demarches led within the international Active and Assisted Living (AAL) Programme endorsing “smart solutions for ageing well” vision. The eHealth solution, based on open source hardware for interoperability and scalability, supports elders to collect biometric information at home and further provides this info to the corresponding caregivers/volunteers when needed in order to take actions accordingly in proper time. The eHealth system, planned according to Systems Engineering methodology, took in consideration Romanian end-user requirements whose verifications were performed via a PoC implementation. Subsequently the concept will become more comprehensive after several co-design sessions planned to be performed also in Hungary and Italy, partner countries in AAL project consortium.
40.
Antonescu, Mihai; Ștefan, Gheorghe M.
Multi-Function Scan Circuit Proceedings Article
In: 2020 International Semiconductor Conference (CAS), pp. 123-126, 2020, ISSN: 2377-0678.
Abstract | Links | BibTeX | Tags: Registers;Acceleration;Switches;Shape;Process control;Pipelines;Multiplexing;scan;reduction;prefix;permute;split
@inproceedings{9268048,
title = {Multi-Function Scan Circuit},
author = {Mihai Antonescu and Gheorghe M. Ștefan},
doi = {10.1109/CAS50358.2020.9268048},
issn = {2377-0678},
year = {2020},
date = {2020-10-01},
booktitle = {2020 International Semiconductor Conference (CAS)},
pages = {123-126},
abstract = {The practice of parallel computing emphasizes frequently used patterns. Some of them can be accelerated using appropriate networks of simple circuits. We propose a solution, based on the frame offered by the Beneš permutation network. It is adapted to efficiently accelerate some of the most used parallel computation patterns: prefix, split, reduction. The cells of the Beneš network associated to a Map pattern of n units are designed to support the additional functions. Two versions are considered: a log-depth pipelined version and a sequential, iterative version.},
keywords = {Registers;Acceleration;Switches;Shape;Process control;Pipelines;Multiplexing;scan;reduction;prefix;permute;split},
pubstate = {published},
tppubtype = {inproceedings}
}
The practice of parallel computing emphasizes frequently used patterns. Some of them can be accelerated using appropriate networks of simple circuits. We propose a solution, based on the frame offered by the Beneš permutation network. It is adapted to efficiently accelerate some of the most used parallel computation patterns: prefix, split, reduction. The cells of the Beneš network associated to a Map pattern of n units are designed to support the additional functions. Two versions are considered: a log-depth pipelined version and a sequential, iterative version.