Bachelor Thesis Description
The goal of the thesis work was the implementation of an AXI interface for the pRISC FPGA accelerator. For this purpose, two modules were implemented. The first was an adaptor for the AXI-Lite protocol to the pRISC current register interface, allowing the pRISC registers to be read from the AXI host. The second module was an AXI master capable of performing reads and writes. The ultimate goal of the project is to replace the current Xillybus interface of the pRISC with a more portable AXI interface.