Overview

The pRISC SIMD Accelerator is a parallel SIMD accelerator architecture designed to operate in conjunction with a general-purpose processor (e.g. Intel, ARM). The pRISC architectural features are as follows:

  • array of RISC-like processing elements (PEs), capable of performing parallel instruction decode and execute on data in a register file or local SRAM memory
  • conditional execution engine
  • reduction adder tree for performing sum-of-all-elements on vectors of data stored in PE local memories
  • local loop sequencer for executing backwards relative jumps (e.g. for loops)
  • IO logic for vector transfer to and from IO FIFOs
  • FIFO-based control and data transfer, capable of seamless integration with external DMA
  • Work in Progress: Run-time reconfiguration capability which allows the application to add/remove PE instructions and change the number of available PEs.

pRISCAcceleratorDiagram

 

Implementation

The pRISC accelerator (128 PEs, 16b operands) has been implemented in two hardware platforms:

  • The ML605 development board, equipped with a Virtex-6 LX240T FPGA, connected via PCIe to a Core i7 Intel CPU
  • The Zedboard development board, equipped with a Zynq 7020 CPU-FPGA SoC

Both pRISC implementations utilize the Xillybus DMA interface to transfer data and code between the host and accelerator, as illustrated in the following figure:

SystemDiagram

Programming the pRISC

Programming the pRISC is achieved with OPINCAA, a macro assembler which enables seamless integration of host and accelerator code in C++. pRISC/OPINCAA code may be compiled with any existing C++ compiler.