Bachelor Thesis Description
The goal of the thesis work was the creation of a verification environment for a FPGA vector processor, of the Connex/pRISC architecture. The thesis specifically targeted the IO (Input/Output) subsystem of the Connex vector processor, utilized to transfer data between the vector processor and main memory, under the control of a host processor. Connex stores to-be-processed data and results, collectively called vectors, in internal memories. Transfers of vectors to and from these memories are handled by the Input/Output subsystem, a subsystem which provides physical and logical translation between a First In First Out (FIFO)-type Xillybus Direct Memory Access (DMA) interface to the system processor, and the local Random-Access Memory (RAM) storage. The IO subsystem utilizes two Xillybus FIFOs: one FIFO transfers vectors from processor to Connex, while the other transfers vectors from Connex to the processor. The verification environment was developed in SystemVerilog utilizing the Universal Verification Methodology class library. Tests were both random and directed, and several important defects were identified and fixed as part of this work.