Introduction

Frequency Scaling is an established technique for adaptive reduction of power in processors. Traditional frequency scaling reduces the processor frequency when the computational load is low, and the optimum frequency is often re-calculated at a pre-determined time period, which is in the millisecond range.

At ARH, we looked at frequency scaling as a method of performance increase, instead of power reduction. The fundamental idea is the following: a processor is a digital circuit consisting of multiple sub-circuits, each of which performs computations related to one (or at most a few) of the instructions in the processor ISA. Some of these sub-circuits are slower than others, and slow down the processor overall, since the maximum frequency of the processor cannot exceed the maximum frequency of any individual sub-circuit. However, if the frequency of the clock signal can be adjusted very finely in very short time intervals (nanoseconds instead of milliseconds) then the processor may be over-clocked when the slow sub-circuits are not in use.

Quality and Efficiency Evaluation

Our team implemented a high-performance clock conditioning circuit which enables a processor clock frequency (or more accurately, the length of the clock period) to be adjusted for each instruction executed. This circuit, which we call the Hybrid Adaptive Clock Manager (HACM) was designed and implemented for Xilinx FPGAs and evaluated against the pRISC SIMD coprocessor. We found an increase of up to 25% in executed instructions per second on synthetic benchmarks.

Publications

Our first endeavor in this field utilized a simple clock multiplexing technique described in the following conference paper:

  • Lucian Petrica, Valeriu Codreanu, and Sorin Cotofana. “VASILE: A reconfigurable vector architecture for instruction level frequency scaling.” Faible Tension Faible Consommation (FTFC), 2013. BibTex Citation:
    @inproceedings{petrica2013vasile,
      title={VASILE: A reconfigurable vector architecture for instruction level frequency scaling},
      author={Petrica, Lucian and Codreanu, Valeriu and Cotofana, Sorin},
      booktitle={Faible Tension Faible Consommation (FTFC), 2013 IEEE},
      pages={1--4},
      year={2013},
      organization={IEEE}
    }

The HACM is described in the following conference paper:

  • A. Gheolbănoiu, L. Petrică and S. Coţofană, “Hybrid adaptive clock management for FPGA processor acceleration,” 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, 2015, pp. 1359-1364. DOI: 10.7873/DATE.2015.0853. BibTex Citation:
    @inproceedings{gheolbuanoiu2015hybrid,
      title={Hybrid adaptive clock management for FPGA processor acceleration},
      author={Gheolb{\u{a}}noiu, Alexandra and Petric{\u{a}}, Lucian and Co{\c{t}}ofan{\u{a}}, Sorin},
      booktitle={Design, Automation \& Test in Europe Conference \& Exhibition (DATE), 2015},
      pages={1359--1364},
      year={2015},
      organization={IEEE}
    }