george-vladut_popescu

Bachelor and Masters degree (Advanced Microelectronics program) in collaboration with the ARH laboratory, under the supervision of Lucian Petrică

Currently studying for a PhD, under the supervision of Gheorghe Ștefan.

Bachelor Thesis Description

The goal of the thesis work was the creation of a software/hardware co-design environment – called OPINCAA-RC – for a FPGA vector processor, in order to reduce the processor power dissipation for certain applications. The starting environment is OPINCAA and the target architecture is a modified Connex accelerator, which utilizes an updated instruction set architecture (ISA) which supports partial and run-time reconfiguration. OPINCAA allows the user to mix host and Connex code in the same C++ source file, much like OpenCL and CUDA. Connex code is structured in a kernel – a section of code in a specific language (Connex macro assembly language), delimited from the rest of the program using keywords. At runtime, the kernel is recognized and processed by OPINCAA and sent to the accelerator.

The reconfigurable Connex architecture allows the deactivation of the processing units that are not utilized in the execution of a certain application. In order to utilize this architecture effectively, besides adapting OPINCAA to the new ISA, a new feature was added: the ability to analyze the application code and decide which processing units are not utilized and may be disabled or completely removed from the Connex structure through partial reconfiguration. The thesis is also a complete guide for porting OPINCAA to future processor architectures and for creating and debugging kernels. To evaluate the environment, we utilized individual tests for each instruction, but also kernels for two applications: SSD (Sum of Squared Differences) and FIR (Finite Impulse Response).

Bachelor thesis full text PDF and slides presentation (in Romanian)

Master Thesis Description

The goal of the MSc thesis work was the creation of a FPGA accelerator for sound source localization from multiple (4 up to 16) digital MEMS microphones. The FPGA accelerator was developed, verified, and evaluated on Xilinx Zynq FPGA devices. Development was performed in Verilog. This work is part of the Deforestation Detection project at ARH.

The software, FPGA code, and scripts are open-source under the GNU GPL v3.0 license, and are available here

Masters thesis full text PDF

Publications

  • 2016
    • Alexandru Gheolbănoiu, George-Vlad Popescu, Lucian Petrică, A Software-Defined FPGA Vector Processor with Application-Aware Reconfiguration, UPB Bulletin Series C, In Press