Bachelor degree work was performed at Amiq Consulting in collaboration with the ARH laboratory, under the supervision of Lucian Petrică (ARH), Stefan Birman (Amiq), and Răzvan Deaconescu (Faculty of Automatic Control and Computers).
Bachelor Thesis Description
The goal of the thesis work was the creation of a verification environment for a FPGA vector processor, of the Connex/pRISC architecture. The thesis specifically targeted the processing unit subsystem of the Connex vector processor, utilized to execute vector instructions. The processing unit subsystem includes several dedicated circuits for local memory access, RISC-type instructions (arithmetic and logical instructions) and CISC-type instructions, such as vector shifting, which is performed in multiple clock cycles utilizing a control automaton. The verification environment was developed in SystemVerilog utilizing the Universal Verification Methodology class library. Tests were both random and directed, and several defects were identified, in both the Verilog implementation of the processor and its specification.