Master’s degree in collaboration with the ARH laboratory, under the supervision of Lucian Petrică, contributing to subjects related to dynamic FPGA reconfiguration of the pRISC (ConnexArray) processor, Cellular Automaton RNGs, and Instruction Level Frequency Scaling

Master’s Thesis Description

  • Project Title: Reconfigurable ConnexArray FPGA Processor
  • Project Description:
    • Design of a highly configurable FPGA based version of the ConnexArray Vector Processor
    • Implementation of said processor on a Xilinx Zynq SoC, enabling co-execution of code on the ARM Processor and the ConnexArray Co-Processor
    • Enhancement of the architecture to allow the usage of Dynamic Partial Reconfiguration, enabling run-time reconfiguration of the Co-Processor’s structure
    • Performance evaluation of the system using different common algorithms, including SSD and FIR Filter

Master thesis full text PDF and slides presentation